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authorJuzhe-Zhong <juzhe.zhong@rivai.ai>2023-11-26 17:13:55 +0800
committerPan Li <pan2.li@intel.com>2023-11-26 17:15:26 +0800
commitec84a1e7a18f65858a1b129ff80cb32e64cf151b (patch)
treea177b5b3662f0bc85f56be03660e01caa82b0702 /gcc/config/riscv/riscv-avlprop.cc
parentbd7f16b43e2afe5bd8429479485b5c70cedbdee6 (diff)
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RISC-V: Disable AVL propagation of slidedown instructions
Re-check again RVV ISA, I find that we can't allow AVL propagation not only for vrgather, but also slidedown instructions. Committed. PR target/112599 gcc/ChangeLog: * config/riscv/riscv-avlprop.cc (avl_can_be_propagated_p): Add slidedown. (vlmax_ta_p): Ditto. (pass_avlprop::get_vlmax_ta_preferred_avl): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/vf_avl-1.c: Adapt test. * gcc.target/riscv/rvv/autovec/pr112599-3.c: New test.
Diffstat (limited to 'gcc/config/riscv/riscv-avlprop.cc')
-rw-r--r--gcc/config/riscv/riscv-avlprop.cc26
1 files changed, 20 insertions, 6 deletions
diff --git a/gcc/config/riscv/riscv-avlprop.cc b/gcc/config/riscv/riscv-avlprop.cc
index 7a741c2..d298f0e 100644
--- a/gcc/config/riscv/riscv-avlprop.cc
+++ b/gcc/config/riscv/riscv-avlprop.cc
@@ -108,17 +108,29 @@ avlprop_type_to_str (enum avlprop_type type)
static bool
avl_can_be_propagated_p (rtx_insn *rinsn)
{
- /* The index of "vrgather dest, source, index" may pick up the
- element which has index >= AVL, so we can't strip the elements
- that has index >= AVL of source register. */
- return get_attr_type (rinsn) != TYPE_VGATHER;
+ /* We can't do AVL propagation when the instruction is potentially
+ touching the element with i > AVL. So, we don't do AVL propagation
+ on these following situations:
+
+ - The index of "vrgather dest, source, index" may pick up the
+ element which has index >= AVL, so we can't strip the elements
+ that has index >= AVL of source register.
+ - The last element of vslide1down is AVL + 1 according to RVV ISA:
+ vstart <= i < vl-1 vd[i] = vs2[i+1] if v0.mask[i] enabled
+ - The last multiple elements of vslidedown can be the element
+ has index >= AVL according to RVV ISA:
+ 0 <= i+OFFSET < VLMAX src[i] = vs2[i+OFFSET]
+ vstart <= i < vl vd[i] = src[i] if v0.mask[i] enabled. */
+ return get_attr_type (rinsn) != TYPE_VGATHER
+ && get_attr_type (rinsn) != TYPE_VSLIDEDOWN
+ && get_attr_type (rinsn) != TYPE_VISLIDE1DOWN
+ && get_attr_type (rinsn) != TYPE_VFSLIDE1DOWN;
}
static bool
vlmax_ta_p (rtx_insn *rinsn)
{
- return vlmax_avl_type_p (rinsn) && tail_agnostic_p (rinsn)
- && avl_can_be_propagated_p (rinsn);
+ return vlmax_avl_type_p (rinsn) && tail_agnostic_p (rinsn);
}
static machine_mode
@@ -271,6 +283,8 @@ pass_avlprop::get_preferred_avl (
rtx
pass_avlprop::get_vlmax_ta_preferred_avl (insn_info *insn) const
{
+ if (!avl_can_be_propagated_p (insn->rtl ()))
+ return NULL_RTX;
int sew = get_sew (insn->rtl ());
enum vlmul_type vlmul = get_vlmul (insn->rtl ());
int ratio = calculate_ratio (sew, vlmul);