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| author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2023-02-10 05:45:44 +0800 |
|---|---|---|
| committer | Kito Cheng <kito.cheng@sifive.com> | 2023-02-12 15:26:24 +0800 |
| commit | 6271a07219a7d764ef59607836c01e0084c3d50c (patch) | |
| tree | e144002776f8d81e2a0ed4b375e3bce9c03ceafd /gcc/config/riscv/predicates.md | |
| parent | 30eedd6a4fccbd3202490ad2dd483bfd1b48201e (diff) | |
| download | gcc-6271a07219a7d764ef59607836c01e0084c3d50c.zip gcc-6271a07219a7d764ef59607836c01e0084c3d50c.tar.gz gcc-6271a07219a7d764ef59607836c01e0084c3d50c.tar.bz2 | |
RISC-V: Add vnsrl/vnsra/vncvt/vmerge/vmv C/C++ support
gcc/ChangeLog:
* config/riscv/constraints.md (Wbr): Remove unused constraint.
* config/riscv/predicates.md: Fix move operand predicate.
* config/riscv/riscv-vector-builtins-bases.cc (class vnshift): New class.
(class vncvt_x): Ditto.
(class vmerge): Ditto.
(class vmv_v): Ditto.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vsra): Ditto.
(vsrl): Ditto.
(vnsrl): Ditto.
(vnsra): Ditto.
(vncvt_x): Ditto.
(vmerge): Ditto.
(vmv_v): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct narrow_alu_def): Ditto.
(struct move_def): Ditto.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_WEXTI_OPS): New variable.
(DEF_RVV_WEXTU_OPS): Ditto
* config/riscv/riscv-vector-builtins.def (x_x_w): Fix type for suffix.
(v_v): Ditto.
(v_x): Ditto.
(x_w): Ditto.
(x): Ditto.
* config/riscv/riscv.cc (riscv_print_operand): Refine ASM printting rule.
* config/riscv/vector-iterators.md (nmsac):New iterator.
(nmsub): New iterator.
* config/riscv/vector.md (@pred_merge<mode>): New pattern.
(@pred_merge<mode>_scalar): New pattern.
(*pred_merge<mode>_scalar): New pattern.
(*pred_merge<mode>_extended_scalar): New pattern.
(@pred_narrow_<optab><mode>): New pattern.
(@pred_narrow_<optab><mode>_scalar): New pattern.
(@pred_trunc<mode>): New pattern.
Diffstat (limited to 'gcc/config/riscv/predicates.md')
| -rw-r--r-- | gcc/config/riscv/predicates.md | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 8d2ccb0..fe2c5ba 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -288,10 +288,9 @@ (match_test "op == CONSTM1_RTX (GET_MODE (op))"))) (define_predicate "vector_merge_operand" - (ior (match_operand 0 "memory_operand") - (ior (match_operand 0 "register_operand") - (match_test "GET_CODE (op) == UNSPEC - && (XINT (op, 1) == UNSPEC_VUNDEF)")))) + (ior (match_operand 0 "register_operand") + (match_test "GET_CODE (op) == UNSPEC + && (XINT (op, 1) == UNSPEC_VUNDEF)"))) (define_predicate "vector_arith_operand" (ior (match_operand 0 "register_operand") |