RISC-V: Support combine extend and reduce sum to widen reduce sum

This patch add combine pattern to combine extend and reduce sum
to widen reduce sum. The pattern in autovec.md was adjusted as
needed. Note that the current vectorization cannot generate reduce
operand which is LMUL=M8, because this means that we need an LMUL=M16
for the extended operand, which is currently not possible. So I've
added VI_QHS_NO_M8 and VF_HS_NO_M8 mode iterator, which exclude
mode which is LMUL=M8.

	PR target/111381

gcc/ChangeLog:

	* config/riscv/autovec-opt.md (*reduc_plus_scal_<mode>):
	New combine pattern.
	(*fold_left_widen_plus_<mode>): Ditto.
	(*mask_len_fold_left_widen_plus_<mode>): Ditto.
	* config/riscv/autovec.md (reduc_plus_scal_<mode>):
	Change from define_expand to define_insn_and_split.
	(fold_left_plus_<mode>): Ditto.
	(mask_len_fold_left_plus_<mode>): Ditto.
	* config/riscv/riscv-v.cc (expand_reduction):
	Support widen reduction.
	* config/riscv/vector-iterators.md (UNSPEC_WREDUC_SUM):
	Add new iterators and attrs.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/widen/widen_reduc-1.c: New test.
	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-1.c: New test.
	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order-2.c: New test.
	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-1.c: New test.
	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_order_run-2.c: New test.
	* gcc.target/riscv/rvv/autovec/widen/widen_reduc_run-1.c: New test.

1 files changed, 49 insertions, 25 deletions

diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 9e05afd..8537b9d 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -2086,14 +2086,20 @@
 ;; - vredxor.vs
 ;; -------------------------------------------------------------------------
 
-(define_expand "reduc_plus_scal_<mode>"
-  [(match_operand:<VEL> 0 "register_operand")
-   (match_operand:VI 1 "register_operand")]
-  "TARGET_VECTOR"
+(define_insn_and_split "reduc_plus_scal_<mode>"
+  [(set (match_operand:<VEL> 0 "register_operand")
+        (unspec:<VEL> [
+             (match_operand:VI 1 "register_operand")
+        ] UNSPEC_REDUC_SUM))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
 {
   riscv_vector::expand_reduction (UNSPEC_REDUC_SUM, operands, CONST0_RTX (<VEL>mode));
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 (define_expand "reduc_smax_scal_<mode>"
   [(match_operand:<VEL> 0 "register_operand")
@@ -2173,15 +2179,21 @@
 ;; - vfredmin.vs
 ;; -------------------------------------------------------------------------
 
-(define_expand "reduc_plus_scal_<mode>"
-  [(match_operand:<VEL> 0 "register_operand")
-   (match_operand:VF 1 "register_operand")]
-  "TARGET_VECTOR"
+(define_insn_and_split "reduc_plus_scal_<mode>"
+  [(set (match_operand:<VEL> 0 "register_operand")
+        (unspec:<VEL> [
+             (match_operand:VF 1 "register_operand")
+        ] UNSPEC_REDUC_SUM_UNORDERED))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
 {
   riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_UNORDERED, operands,
                                   CONST0_RTX (<VEL>mode));
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 (define_expand "reduc_smax_scal_<mode>"
   [(match_operand:<VEL> 0 "register_operand")
@@ -2215,27 +2227,38 @@
 ;; -------------------------------------------------------------------------
 
 ;; Unpredicated in-order FP reductions.
-(define_expand "fold_left_plus_<mode>"
-  [(match_operand:<VEL> 0 "register_operand")
-   (match_operand:<VEL> 1 "register_operand")
-   (match_operand:VF 2 "register_operand")]
-  "TARGET_VECTOR"
+(define_insn_and_split "fold_left_plus_<mode>"
+  [(set (match_operand:<VEL> 0 "register_operand")
+        (unspec:<VEL> [
+             (match_operand:VF 2 "register_operand")
+             (match_operand:<VEL> 1 "register_operand")
+        ] UNSPEC_REDUC_SUM_ORDERED))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
 {
   riscv_vector::expand_reduction (UNSPEC_REDUC_SUM_ORDERED, operands,
 				  operands[1],
 				  riscv_vector::reduction_type::FOLD_LEFT);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; Predicated in-order FP reductions.
-(define_expand "mask_len_fold_left_plus_<mode>"
-  [(match_operand:<VEL> 0 "register_operand")
-   (match_operand:<VEL> 1 "register_operand")
-   (match_operand:VF 2 "register_operand")
-   (match_operand:<VM> 3 "vector_mask_operand")
-   (match_operand 4 "autovec_length_operand")
-   (match_operand 5 "const_0_operand")]
-  "TARGET_VECTOR"
+(define_insn_and_split "mask_len_fold_left_plus_<mode>"
+  [(set (match_operand:<VEL> 0 "register_operand")
+        (unspec:<VEL> [
+          (match_operand:VF 2 "register_operand")
+          (match_operand:<VEL> 1 "register_operand")
+          (match_operand:<VM> 3 "vector_mask_operand")
+          (match_operand 4 "autovec_length_operand")
+          (match_operand 5 "const_0_operand")
+        ] UNSPEC_REDUC_SUM_ORDERED))]
+  "TARGET_VECTOR && can_create_pseudo_p ()"
+  "#"
+  "&& 1"
+  [(const_int 0)]
 {
   if (rtx_equal_p (operands[4], const0_rtx))
     emit_move_insn (operands[0], operands[1]);
@@ -2244,7 +2267,8 @@
 				    operands[1],
 				    riscv_vector::reduction_type::MASK_LEN_FOLD_LEFT);
   DONE;
-})
+}
+[(set_attr "type" "vector")])
 
 ;; -------------------------------------------------------------------------
 ;; ---- [INT,FP] Extract active element