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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-09-19 19:01:24 +0800 |
|---|---|---|
| committer | Lehua Ding <lehua.ding@rivai.ai> | 2023-09-19 19:27:42 +0800 |
| commit | 5b945243c77e3ecd8dfab4b8b44f21daa3de8fe1 (patch) | |
| tree | 06826815b5263cfa2d9e270985cce849ae3abf54 /gcc/config/riscv/autovec.md | |
| parent | 047269320d433e4024fcb3580f638bcb2aca7664 (diff) | |
| download | gcc-5b945243c77e3ecd8dfab4b8b44f21daa3de8fe1.zip gcc-5b945243c77e3ecd8dfab4b8b44f21daa3de8fe1.tar.gz gcc-5b945243c77e3ecd8dfab4b8b44f21daa3de8fe1.tar.bz2 | |
RISC-V: Support VLS unary floating-point patterns
Extend current VLA patterns with VLS modes.
Regression all passed.
gcc/ChangeLog:
* config/riscv/autovec.md: Extend VLS modes.
* config/riscv/vector.md: Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/vls/def.h: Add unary test.
* gcc.target/riscv/rvv/autovec/vls/neg-2.c: New test.
Diffstat (limited to 'gcc/config/riscv/autovec.md')
| -rw-r--r-- | gcc/config/riscv/autovec.md | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 769ef6d..75ed7ae 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1031,9 +1031,9 @@ ;; - vfneg.v/vfabs.v ;; ------------------------------------------------------------------------------- (define_insn_and_split "<optab><mode>2" - [(set (match_operand:VF 0 "register_operand") - (any_float_unop_nofrm:VF - (match_operand:VF 1 "register_operand")))] + [(set (match_operand:V_VLSF 0 "register_operand") + (any_float_unop_nofrm:V_VLSF + (match_operand:V_VLSF 1 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" @@ -1052,9 +1052,9 @@ ;; - vfsqrt.v ;; ------------------------------------------------------------------------------- (define_insn_and_split "<optab><mode>2" - [(set (match_operand:VF 0 "register_operand") - (any_float_unop:VF - (match_operand:VF 1 "register_operand")))] + [(set (match_operand:V_VLSF 0 "register_operand") + (any_float_unop:V_VLSF + (match_operand:V_VLSF 1 "register_operand")))] "TARGET_VECTOR && can_create_pseudo_p ()" "#" "&& 1" |