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| author | Juzhe-Zhong <juzhe.zhong@rivai.ai> | 2023-11-10 11:33:16 +0800 |
|---|---|---|
| committer | Pan Li <pan2.li@intel.com> | 2023-11-10 16:16:41 +0800 |
| commit | 072a409803a270fd3e8f8aa1b4f9bb8e83789b85 (patch) | |
| tree | a4db98cbd61ecfe6cc67ccb06317ac6956e95885 /gcc/config/riscv/autovec.md | |
| parent | 040e5b0edbca861196d9e2ea2af5e805769c8d5d (diff) | |
| download | gcc-072a409803a270fd3e8f8aa1b4f9bb8e83789b85.zip gcc-072a409803a270fd3e8f8aa1b4f9bb8e83789b85.tar.gz gcc-072a409803a270fd3e8f8aa1b4f9bb8e83789b85.tar.bz2 | |
RISC-V: Robustify vec_init pattern[NFC]
Although current GCC didn't cause ICE when I create FP16 vec_init case
with -march=rv64gcv (no ZVFH), current vec_init pattern looks wrong.
Since V_VLS FP16 predicate is TARGET_VECTOR_ELEN_FP_16, wheras vec_init
needs vfslide1down/vfslide1up.
It makes more sense to robustify the vec_init patterns which split them
into 2 patterns (one is integer, the other is float) like other autovectorization patterns.
gcc/ChangeLog:
* config/riscv/autovec.md (vec_init<mode><vel>): Split patterns.
Diffstat (limited to 'gcc/config/riscv/autovec.md')
| -rw-r--r-- | gcc/config/riscv/autovec.md | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 33722ea..868b47c 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -373,7 +373,19 @@ ;; ------------------------------------------------------------------------- (define_expand "vec_init<mode><vel>" - [(match_operand:V_VLS 0 "register_operand") + [(match_operand:V_VLSI 0 "register_operand") + (match_operand 1 "")] + "TARGET_VECTOR" + { + riscv_vector::expand_vec_init (operands[0], operands[1]); + DONE; + } +) + +;; We split RVV floating-point because we are going to +;; use vfslide1down/vfslide1up for FP16 which need TARGET_ZVFH. +(define_expand "vec_init<mode><vel>" + [(match_operand:V_VLSF 0 "register_operand") (match_operand 1 "")] "TARGET_VECTOR" { |