alpha.c (alpha_preferred_reload_class, [...]): Avoid C++ keywords.

	* config/alpha/alpha.c (alpha_preferred_reload_class,
	alpha_secondary_reload, alpha_emit_set_const_1, function_value,
	alpha_output_mi_thunk_osf): Avoid C++ keywords.
	* config/arm/arm.c (output_move_vfp, output_move_neon): Likewise.
	* config/arm/arm.md: Likewise.
	* config/avr/avr-protos.h (preferred_reload_class,
	test_hard_reg_class, avr_simplify_comparison_p,
	out_shift_with_cnt, class_max_nregs): Likewise.
	* config/avr/avr.c (class_max_nregs, avr_simplify_comparison_p,
	output_movqi, output_movhi, output_movsisf, out_shift_with_cnt,
	preferred_reload_class, test_hard_reg_class): Likewise.
	* config/bfin/bfin.c (legitimize_pic_address, hard_regno_mode_ok,
	bfin_memory_move_cost, bfin_secondary_reload,
	bfin_output_mi_thunk): Likewise.
	* config/crx/crx.c (crx_secondary_reload_class,
	crx_memory_move_cost): Likewise.
	* config/frv/frv-protos.h (frv_secondary_reload_class,
	frv_class_likely_spilled_p, frv_class_max_nregs): Likewise.
	* config/frv/frv.c (frv_override_options, frv_alloc_temp_reg,
	frv_secondary_reload_class, frv_class_likely_spilled_p,
	frv_class_max_nregs): Likewise.
	* config/h8300/h8300.c (h8300_classify_operand,
	h8300_unary_length, h8300_bitfield_length, h8300_asm_insn_count):
	Likewise.
	* config/i386/winnt.c (i386_pe_declare_function_type): Likewise.
	* config/ia64/ia64.c (ia64_preferred_reload_class,
	ia64_secondary_reload_class, ia64_output_mi_thunk): Likewise.
	* config/iq2000/iq2000.c (gen_int_relational): Likewise.
	* config/m32c/m32c.c (class_can_hold_mode, m32c_output_compare):
	Likewise.
	* config/m68hc11/m68hc11.c (preferred_reload_class,
	m68hc11_memory_move_cost): Likewise.
	* config/mcore/mcore.c (mcore_secondary_reload_class,
	mcore_reload_class): Likewise.
	* config/mips/mips.c (mips_hard_regno_mode_ok_p,
	mips_class_max_nregs, mips_cannot_change_mode_class,
	mips_preferred_reload_class, mips_secondary_reload_class,
	mips_output_mi_thunk): Likewise.
	* config/mmix/mmix.c (mmix_preferred_reload_class,
	mmix_preferred_output_reload_class, mmix_secondary_reload_class):
	Likewise.
	* config/mn10300/mn10300.c (mn10300_secondary_reload_class):
	Likewise.
	* config/pa/pa.c (pa_secondary_reload, pa_combine_instructions,
	pa_can_combine_p, pa_cannot_change_mode_class): Likewise.
	* config/pa/pa.h (LEGITIMIZE_RELOAD_ADDRESS): Likewise.
	* config/rs6000/rs6000.c (paired_expand_vector_init,
	rs6000_secondary_reload_class, rs6000_output_mi_thunk,
	compare_section_name, rs6000_memory_move_cost): Likewise.
	* config/s390/s390.c (s390_emit_compare_and_swap,
	s390_preferred_reload_class, s390_secondary_reload,
	legitimize_pic_address, legitimize_tls_address,
	legitimize_reload_address, s390_expand_cs_hqi, s390_expand_atomic,
	s390_class_max_nregs): Likewise.
	* config/s390/s390.h (LEGITIMIZE_RELOAD_ADDRESS): Likewise.
	* config/s390/s390.md: Likewise.
	* config/score/score-protos.h (score_secondary_reload_class,
	score_preferred_reload_class): Likewise.
	* config/score/score.c (score_preferred_reload_class,
	score_secondary_reload_class): Likewise.
	* config/score/score3.c (score3_output_mi_thunk,
	score3_preferred_reload_class, score3_secondary_reload_class,
	score3_hard_regno_mode_ok): Likewise.
	* config/score/score3.h (score3_preferred_reload_class,
	score3_secondary_reload_class): Likewise.
	* config/score/score7.c (score7_output_mi_thunk,
	score7_preferred_reload_class, score7_secondary_reload_class,
	score7_hard_regno_mode_ok): Likewise.
	* config/score/score7.h (score7_preferred_reload_class,
	score7_secondary_reload_class): Likewise.
	* config/sh/sh.c (prepare_move_operands, output_far_jump,
	output_branchy_insn, add_constant, gen_block_redirect,
	sh_insn_length_adjustment, sh_cannot_change_mode_class,
	sh_output_mi_thunk, replace_n_hard_rtx, sh_secondary_reload):
	Likewise.
	* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
	* config/stormy16/stormy16.c (xstormy16_output_cbranch_hi,
	xstormy16_output_cbranch_si, xstormy16_secondary_reload_class,
	xstormy16_preferred_reload_class): Likewise.
	* config/xtensa/xtensa.c (xtensa_expand_compare_and_swap,
	xtensa_expand_atomic, override_options,
	xtensa_preferred_reload_class, xtensa_secondary_reload_class):
	Likewise.
	* reorg.c (try_merge_delay_insns): Likewise.
	* tree.c (merge_dllimport_decl_attributes): Likewise.

	* config/frv/frv.c (frv_print_operand): Change isalpha to ISALPHA.

From-SVN: r138813

2 files changed, 30 insertions, 30 deletions

diff --git a/gcc/config/pa/pa.c b/gcc/config/pa/pa.c
index 76d84ba..9ff778b 100644
--- a/gcc/config/pa/pa.c
+++ b/gcc/config/pa/pa.c
@@ -5684,19 +5684,19 @@ output_arg_descriptor (rtx call_insn)
 }
 
 static enum reg_class
-pa_secondary_reload (bool in_p, rtx x, enum reg_class class,
+pa_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
 		     enum machine_mode mode, secondary_reload_info *sri)
 {
   int is_symbolic, regno;
 
   /* Handle the easy stuff first.  */
-  if (class == R1_REGS)
+  if (rclass == R1_REGS)
     return NO_REGS;
 
   if (REG_P (x))
     {
       regno = REGNO (x);
-      if (class == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER)
+      if (rclass == BASE_REG_CLASS && regno < FIRST_PSEUDO_REGISTER)
 	return NO_REGS;
     }
   else
@@ -5712,7 +5712,7 @@ pa_secondary_reload (bool in_p, rtx x, enum reg_class class,
      generation requires %r1 as a scratch register.  */
   if (flag_pic
       && (mode == SImode || mode == DImode)
-      && FP_REG_CLASS_P (class)
+      && FP_REG_CLASS_P (rclass)
       && (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
     {
       sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
@@ -5735,7 +5735,7 @@ pa_secondary_reload (bool in_p, rtx x, enum reg_class class,
      memory loads and stores.  */
   if ((regno >= FIRST_PSEUDO_REGISTER || regno == -1)
       && GET_MODE_CLASS (mode) == MODE_INT
-      && FP_REG_CLASS_P (class))
+      && FP_REG_CLASS_P (rclass))
     {
       /* Reload passes (mem:SI (reg/f:DI 30 %r30) when it wants to check
 	 the secondary reload needed for a pseudo.  It never passes a
@@ -5767,7 +5767,7 @@ pa_secondary_reload (bool in_p, rtx x, enum reg_class class,
 
   /* We need a secondary register (GPR) for copies between the SAR
      and anything other than a general register.  */
-  if (class == SHIFT_REGS && (regno <= 0 || regno >= 32))
+  if (rclass == SHIFT_REGS && (regno <= 0 || regno >= 32))
     {
       sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode];
       return NO_REGS;
@@ -5777,7 +5777,7 @@ pa_secondary_reload (bool in_p, rtx x, enum reg_class class,
      well as secondary memory.  */
   if (regno >= 0 && regno < FIRST_PSEUDO_REGISTER
       && (REGNO_REG_CLASS (regno) == SHIFT_REGS
-      && FP_REG_CLASS_P (class)))
+      && FP_REG_CLASS_P (rclass)))
     {
       sri->icode = in_p ? reload_in_optab[mode] : reload_out_optab[mode];
       return NO_REGS;
@@ -8831,7 +8831,7 @@ pa_reorg (void)
 static void
 pa_combine_instructions (void)
 {
-  rtx anchor, new;
+  rtx anchor, new_rtx;
 
   /* This can get expensive since the basic algorithm is on the
      order of O(n^2) (or worse).  Only do it for -O2 or higher
@@ -8843,8 +8843,8 @@ pa_combine_instructions (void)
      may be combined with "floating" insns.  As the name implies,
      "anchor" instructions don't move, while "floating" insns may
      move around.  */
-  new = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
-  new = make_insn_raw (new);
+  new_rtx = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, NULL_RTX, NULL_RTX));
+  new_rtx = make_insn_raw (new_rtx);
 
   for (anchor = get_insns (); anchor; anchor = NEXT_INSN (anchor))
     {
@@ -8900,7 +8900,7 @@ pa_combine_instructions (void)
 		{
 		  /* If ANCHOR and FLOATER can be combined, then we're
 		     done with this pass.  */
-		  if (pa_can_combine_p (new, anchor, floater, 0,
+		  if (pa_can_combine_p (new_rtx, anchor, floater, 0,
 					SET_DEST (PATTERN (floater)),
 					XEXP (SET_SRC (PATTERN (floater)), 0),
 					XEXP (SET_SRC (PATTERN (floater)), 1)))
@@ -8912,7 +8912,7 @@ pa_combine_instructions (void)
 		{
 		  if (GET_CODE (SET_SRC (PATTERN (floater))) == PLUS)
 		    {
-		      if (pa_can_combine_p (new, anchor, floater, 0,
+		      if (pa_can_combine_p (new_rtx, anchor, floater, 0,
 					    SET_DEST (PATTERN (floater)),
 					XEXP (SET_SRC (PATTERN (floater)), 0),
 					XEXP (SET_SRC (PATTERN (floater)), 1)))
@@ -8920,7 +8920,7 @@ pa_combine_instructions (void)
 		    }
 		  else
 		    {
-		      if (pa_can_combine_p (new, anchor, floater, 0,
+		      if (pa_can_combine_p (new_rtx, anchor, floater, 0,
 					    SET_DEST (PATTERN (floater)),
 					    SET_SRC (PATTERN (floater)),
 					    SET_SRC (PATTERN (floater))))
@@ -8962,7 +8962,7 @@ pa_combine_instructions (void)
 		    {
 		      /* If ANCHOR and FLOATER can be combined, then we're
 			 done with this pass.  */
-		      if (pa_can_combine_p (new, anchor, floater, 1,
+		      if (pa_can_combine_p (new_rtx, anchor, floater, 1,
 					    SET_DEST (PATTERN (floater)),
 					    XEXP (SET_SRC (PATTERN (floater)),
 						  0),
@@ -9021,7 +9021,7 @@ pa_combine_instructions (void)
 }
 
 static int
-pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
+pa_can_combine_p (rtx new_rtx, rtx anchor, rtx floater, int reversed, rtx dest,
 		  rtx src1, rtx src2)
 {
   int insn_code_number;
@@ -9034,12 +9034,12 @@ pa_can_combine_p (rtx new, rtx anchor, rtx floater, int reversed, rtx dest,
      If the pattern doesn't match or the constraints
      aren't met keep searching for a suitable floater
      insn.  */
-  XVECEXP (PATTERN (new), 0, 0) = PATTERN (anchor);
-  XVECEXP (PATTERN (new), 0, 1) = PATTERN (floater);
-  INSN_CODE (new) = -1;
-  insn_code_number = recog_memoized (new);
+  XVECEXP (PATTERN (new_rtx), 0, 0) = PATTERN (anchor);
+  XVECEXP (PATTERN (new_rtx), 0, 1) = PATTERN (floater);
+  INSN_CODE (new_rtx) = -1;
+  insn_code_number = recog_memoized (new_rtx);
   if (insn_code_number < 0
-      || (extract_insn (new), ! constrain_operands (1)))
+      || (extract_insn (new_rtx), ! constrain_operands (1)))
     return 0;
 
   if (reversed)
@@ -9652,11 +9652,11 @@ pa_hpux_file_end (void)
 #endif
 
 /* Return true if a change from mode FROM to mode TO for a register
-   in register class CLASS is invalid.  */
+   in register class RCLASS is invalid.  */
 
 bool
 pa_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
-			     enum reg_class class)
+			     enum reg_class rclass)
 {
   if (from == to)
     return false;
@@ -9674,7 +9674,7 @@ pa_cannot_change_mode_class (enum machine_mode from, enum machine_mode to,
      On the 64-bit target, this conflicts with the definition of
      LOAD_EXTEND_OP.  Thus, we can't allow changing between modes
      with different sizes in the floating-point registers.  */
-  if (MAYBE_FP_REG_CLASS_P (class))
+  if (MAYBE_FP_REG_CLASS_P (rclass))
     return true;
 
   /* HARD_REGNO_MODE_OK places modes with sizes larger than a word
diff --git a/gcc/config/pa/pa.h b/gcc/config/pa/pa.h
index 22cd9f3..610bcf5d 100644
--- a/gcc/config/pa/pa.h
+++ b/gcc/config/pa/pa.h
@@ -1377,7 +1377,7 @@ extern int may_call_alloca;
 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) 	\
 do { 									\
   long offset, newoffset, mask;						\
-  rtx new, temp = NULL_RTX;						\
+  rtx new_rtx, temp = NULL_RTX;						\
 									\
   mask = (GET_MODE_CLASS (MODE) == MODE_FLOAT				\
 	  ? (INT14_OK_STRICT ? 0x3fff : 0x1f) : 0x3fff);		\
@@ -1386,14 +1386,14 @@ do { 									\
     temp = simplify_binary_operation (PLUS, Pmode,			\
 				      XEXP (AD, 0), XEXP (AD, 1));	\
 									\
-  new = temp ? temp : AD;						\
+  new_rtx = temp ? temp : AD;						\
 									\
   if (optimize								\
-      && GET_CODE (new) == PLUS						\
-      && GET_CODE (XEXP (new, 0)) == REG				\
-      && GET_CODE (XEXP (new, 1)) == CONST_INT)				\
+      && GET_CODE (new_rtx) == PLUS						\
+      && GET_CODE (XEXP (new_rtx, 0)) == REG				\
+      && GET_CODE (XEXP (new_rtx, 1)) == CONST_INT)				\
     {									\
-      offset = INTVAL (XEXP ((new), 1));				\
+      offset = INTVAL (XEXP ((new_rtx), 1));				\
 									\
       /* Choose rounding direction.  Round up if we are >= halfway.  */	\
       if ((offset & mask) >= ((mask + 1) / 2))				\
@@ -1409,7 +1409,7 @@ do { 									\
 									\
       if (newoffset != 0 && VAL_14_BITS_P (newoffset))			\
 	{								\
-	  temp = gen_rtx_PLUS (Pmode, XEXP (new, 0),			\
+	  temp = gen_rtx_PLUS (Pmode, XEXP (new_rtx, 0),			\
 			       GEN_INT (newoffset));			\
 	  AD = gen_rtx_PLUS (Pmode, temp, GEN_INT (offset - newoffset));\
 	  push_reload (XEXP (AD, 0), 0, &XEXP (AD, 0), 0,		\