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| author | Jozef Lawrynowicz <jozef.l@mittosystems.com> | 2020-11-13 15:35:52 +0000 |
|---|---|---|
| committer | Jozef Lawrynowicz <jozef.l@mittosystems.com> | 2020-11-13 15:36:30 +0000 |
| commit | 54896b10dbe1d4ac90f097d566b7aa14807cec08 (patch) | |
| tree | 06e411434272c328ecedcba249215873ea875e40 /gcc/config/msp430 | |
| parent | 546c8f955804ad74b0382b012f64e621a02eebde (diff) | |
| download | gcc-54896b10dbe1d4ac90f097d566b7aa14807cec08.zip gcc-54896b10dbe1d4ac90f097d566b7aa14807cec08.tar.gz gcc-54896b10dbe1d4ac90f097d566b7aa14807cec08.tar.bz2 | |
MSP430: Implement TARGET_INSN_COST
The length of an insn can be used to calculate its cost, when optimizing
for size. When optimizing for speed, this is a good estimate, since the
cycle cost of an MSP430 instruction increases with its length.
gcc/ChangeLog:
* config/msp430/msp430.c (TARGET_INSN_COST): Define.
(msp430_insn_cost): New function.
* config/msp430/msp430.h (BRANCH_COST): Define.
(LOGICAL_OP_NON_SHORT_CIRCUIT): Define.
gcc/testsuite/ChangeLog:
* gcc.target/msp430/rtx-cost-O3-default.c: New test.
* gcc.target/msp430/rtx-cost-O3-f5series.c: New test.
* gcc.target/msp430/rtx-cost-Os-default.c: New test.
* gcc.target/msp430/rtx-cost-Os-f5series.c: New test.
Diffstat (limited to 'gcc/config/msp430')
| -rw-r--r-- | gcc/config/msp430/msp430.c | 25 | ||||
| -rw-r--r-- | gcc/config/msp430/msp430.h | 8 |
2 files changed, 28 insertions, 5 deletions
diff --git a/gcc/config/msp430/msp430.c b/gcc/config/msp430/msp430.c index cc3472e..e98de8d 100644 --- a/gcc/config/msp430/msp430.c +++ b/gcc/config/msp430/msp430.c @@ -1181,11 +1181,6 @@ msp430_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, return 2 * cost; } -/* BRANCH_COST - Changing from the default of 1 doesn't affect code generation, presumably - because there are no conditional move insns - when a condition is involved, - the only option is to use a cbranch. */ - /* For X, which must be a MEM RTX, return TRUE if it is an indirect memory reference, @Rn or @Rn+. */ static bool @@ -1650,6 +1645,26 @@ msp430_rtx_costs (rtx x, return false; } } + +#undef TARGET_INSN_COST +#define TARGET_INSN_COST msp430_insn_cost + +static int +msp430_insn_cost (rtx_insn *insn, bool speed ATTRIBUTE_UNUSED) +{ + if (recog_memoized (insn) < 0) + return 0; + + /* The returned cost must be relative to COSTS_N_INSNS (1). An insn with a + length of 2 bytes is the smallest possible size and so must be equivalent + to COSTS_N_INSNS (1). */ + return COSTS_N_INSNS (get_attr_length (insn) / 2); + + /* FIXME Add more detailed costs when optimizing for speed. + For now the length of the instruction is a good approximiation and roughly + correlates with cycle cost. */ +} + /* Function Entry and Exit */ diff --git a/gcc/config/msp430/msp430.h b/gcc/config/msp430/msp430.h index c2fcaef..049151e 100644 --- a/gcc/config/msp430/msp430.h +++ b/gcc/config/msp430/msp430.h @@ -243,6 +243,14 @@ extern const char *msp430_get_linker_devices_include_path (int, const char **); #define HAS_LONG_COND_BRANCH 0 #define HAS_LONG_UNCOND_BRANCH 0 +/* The cost of a branch sequence is roughly 3 "cheap" instructions. */ +#define BRANCH_COST(speed_p, predictable_p) 3 + +/* Override the default BRANCH_COST heuristic to indicate that it is preferable + to retain short-circuit operations, this results in significantly better + codesize and performance. */ +#define LOGICAL_OP_NON_SHORT_CIRCUIT 0 + #define LOAD_EXTEND_OP(M) ZERO_EXTEND #define WORD_REGISTER_OPERATIONS 1 |