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| author | Richard Sandiford <richard@codesourcery.com> | 2006-10-30 18:18:03 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2006-10-30 18:18:03 +0000 |
| commit | e1efef1ef15487a5a4056234db644557ba61cec6 (patch) | |
| tree | 8c5890a6b08a48d47660460d890cce4626f40046 /gcc/config/mips | |
| parent | 8ec2ac7b26d6311dca191f2985053215a3c9a794 (diff) | |
| download | gcc-e1efef1ef15487a5a4056234db644557ba61cec6.zip gcc-e1efef1ef15487a5a4056234db644557ba61cec6.tar.gz gcc-e1efef1ef15487a5a4056234db644557ba61cec6.tar.bz2 | |
mips.md (mul<mode>3): Split into...
gcc/
* config/mips/mips.md (mul<mode>3): Split into...
(mulsi3, muldi3): ...these separate patterns.
From-SVN: r118190
Diffstat (limited to 'gcc/config/mips')
| -rw-r--r-- | gcc/config/mips/mips.md | 32 |
1 files changed, 22 insertions, 10 deletions
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 6613871..8a2e44a 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -1008,19 +1008,31 @@ ;; These processors have PRId values of 0x00004220 and 0x00004300, ;; respectively. -(define_expand "mul<mode>3" - [(set (match_operand:GPR 0 "register_operand") - (mult:GPR (match_operand:GPR 1 "register_operand") - (match_operand:GPR 2 "register_operand")))] +(define_expand "mulsi3" + [(set (match_operand:SI 0 "register_operand") + (mult:SI (match_operand:SI 1 "register_operand") + (match_operand:SI 2 "register_operand")))] "" { - if (<MODE>mode == SImode && ISA_HAS_MUL3) - emit_insn (gen_mul<mode>3_mult3 (operands[0], operands[1], operands[2])); - else if (!TARGET_FIX_R4000) - emit_insn (gen_mul<mode>3_internal (operands[0], operands[1], - operands[2])); + if (ISA_HAS_MUL3) + emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2])); + else if (TARGET_FIX_R4000) + emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2])); + else + emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2])); + DONE; +}) + +(define_expand "muldi3" + [(set (match_operand:DI 0 "register_operand") + (mult:DI (match_operand:DI 1 "register_operand") + (match_operand:DI 2 "register_operand")))] + "TARGET_64BIT" +{ + if (TARGET_FIX_R4000) + emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2])); else - emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2])); + emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2])); DONE; }) |