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| author | David Daney <ddaney@caviumnetworks.com> | 2009-07-10 22:49:52 +0000 |
|---|---|---|
| committer | David Daney <daney@gcc.gnu.org> | 2009-07-10 22:49:52 +0000 |
| commit | b96c5923d4deaf4d37b89b40ff5f6760d22b5ea3 (patch) | |
| tree | e846e50d187b33820a2ae16a58b477f3b1568603 /gcc/config/mips | |
| parent | 5bde96d27e87d819a33236ad3a3ee718fe633d37 (diff) | |
| download | gcc-b96c5923d4deaf4d37b89b40ff5f6760d22b5ea3.zip gcc-b96c5923d4deaf4d37b89b40ff5f6760d22b5ea3.tar.gz gcc-b96c5923d4deaf4d37b89b40ff5f6760d22b5ea3.tar.bz2 | |
re PR target/39079 (MIPS: __builtin___clear_cache() broken on SMP ISA_HAS_SYNCI systems.)
2009-07-10 David Daney <ddaney@caviumnetworks.com>
PR target/39079
* testsuite/gcc.target/mips/mips.exp: Make -msynci a known option.
* gcc.target/mips/clear-cache-1.c (dg-options): Add -msynci.
2009-07-10 David Daney <ddaney@caviumnetworks.com>
PR target/39079
* config.gcc (supported_defaults): Add synci.
(with_synci): Add validation.
(all_defaults): Add synci.
* config/mips/mips.md (clear_cache): Use TARGET_SYNCI instead of
ISA_HAS_SYNCI.
(synci): Same.
* config/mips/mips.opt (msynci): New option.
* config/mips/mips.c (mips_override_options): Warn on use of
-msynci for targets that do now support it.
* gcc/config/mips/mips.h (OPTION_DEFAULT_SPECS): Add a default for
msynci.
* gcc/doc/invoke.texi (-msynci): Document the new option.
* doc/install.texi (--with-synci): Document the new option.
From-SVN: r149500
Diffstat (limited to 'gcc/config/mips')
| -rw-r--r-- | gcc/config/mips/mips.c | 7 | ||||
| -rw-r--r-- | gcc/config/mips/mips.h | 3 | ||||
| -rw-r--r-- | gcc/config/mips/mips.md | 4 | ||||
| -rw-r--r-- | gcc/config/mips/mips.opt | 4 |
4 files changed, 15 insertions, 3 deletions
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 3615892..4a10fb4 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -14524,6 +14524,13 @@ mips_override_options (void) : !TARGET_BRANCHLIKELY)) sorry ("%qs requires branch-likely instructions", "-mfix-r10000"); + if (TARGET_SYNCI && !ISA_HAS_SYNCI) + { + warning (0, "the %qs architecture does not support the synci " + "instruction", mips_arch_info->name); + target_flags &= ~MASK_SYNCI; + } + /* Save base state of options. */ mips_base_target_flags = target_flags; mips_base_schedule_insns = flag_schedule_insns; diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index c8ea605..a3ab2f8 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -787,7 +787,8 @@ enum mips_code_readable_setting { {"float", "%{!msoft-float:%{!mhard-float:-m%(VALUE)-float}}" }, \ {"divide", "%{!mdivide-traps:%{!mdivide-breaks:-mdivide-%(VALUE)}}" }, \ {"llsc", "%{!mllsc:%{!mno-llsc:-m%(VALUE)}}" }, \ - {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" } + {"mips-plt", "%{!mplt:%{!mno-plt:-m%(VALUE)}}" }, \ + {"synci", "%{!msynci:%{!mno-synci:-m%(VALUE)}}" } /* A spec that infers the -mdsp setting from an -march argument. */ diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 46e7afa..3c42b46 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4728,7 +4728,7 @@ "" " { - if (ISA_HAS_SYNCI) + if (TARGET_SYNCI) { mips_expand_synci_loop (operands[0], operands[1]); emit_insn (gen_sync ()); @@ -4753,7 +4753,7 @@ (define_insn "synci" [(unspec_volatile [(match_operand 0 "pmode_register_operand" "d")] UNSPEC_SYNCI)] - "ISA_HAS_SYNCI" + "TARGET_SYNCI" "synci\t0(%0)") (define_insn "rdhwr_synci_step_<mode>" diff --git a/gcc/config/mips/mips.opt b/gcc/config/mips/mips.opt index 9016754..9038125 100644 --- a/gcc/config/mips/mips.opt +++ b/gcc/config/mips/mips.opt @@ -268,6 +268,10 @@ msym32 Target Report Var(TARGET_SYM32) Assume all symbols have 32-bit values +msynci +Target Report Mask(SYNCI) +Use synci instruction to invalidate i-cache + mtune= Target RejectNegative Joined Var(mips_tune_string) -mtune=PROCESSOR Optimize the output for PROCESSOR |