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| author | Uros Bizjak <uros@gcc.gnu.org> | 2008-11-18 23:00:12 +0100 |
|---|---|---|
| committer | Uros Bizjak <uros@gcc.gnu.org> | 2008-11-18 23:00:12 +0100 |
| commit | 8afb060511297809fdd2a8453f2919d57fc5d53d (patch) | |
| tree | 6493cf4ded1ea6c67dad3803b2c68db31a8f9fa6 /gcc/config/mips | |
| parent | 0a4a51c75b941c517d8ac26dfdd92469bc0f621a (diff) | |
| download | gcc-8afb060511297809fdd2a8453f2919d57fc5d53d.zip gcc-8afb060511297809fdd2a8453f2919d57fc5d53d.tar.gz gcc-8afb060511297809fdd2a8453f2919d57fc5d53d.tar.bz2 | |
re PR target/37362 (Bootstrap broken on mipsisa64r2-linux-gcc)
PR target/37362
* config/mips/mips.md (move_doubleword_fpr<mode>): Check that "high"
is a register or zero operand in the correct mode before generating
mtch1 insn or a register operand in the correct mode before generating
mfch1 insn.
(mtch1<mode>): Correct operand 1 predicate to reg_or_0_operand.
testsuite/ChangeLog:
PR target/37362
* gcc.target/mips/pr37362.c: New test.
From-SVN: r141978
Diffstat (limited to 'gcc/config/mips')
| -rw-r--r-- | gcc/config/mips/mips.md | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 92e637c..22fcc88 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -4508,7 +4508,7 @@ rtx low = mips_subword (operands[1], 0); rtx high = mips_subword (operands[1], 1); emit_insn (gen_load_low<mode> (operands[0], low)); - if (ISA_HAS_MXHC1) + if (ISA_HAS_MXHC1 && reg_or_0_operand (high, <HALFMODE>mode)) emit_insn (gen_mthc1<mode> (operands[0], high, operands[0])); else emit_insn (gen_load_high<mode> (operands[0], high, operands[0])); @@ -4518,7 +4518,7 @@ rtx low = mips_subword (operands[0], 0); rtx high = mips_subword (operands[0], 1); emit_insn (gen_store_word<mode> (low, operands[1], const0_rtx)); - if (ISA_HAS_MXHC1) + if (ISA_HAS_MXHC1 && register_operand (high, <HALFMODE>mode)) emit_insn (gen_mfhc1<mode> (high, operands[1])); else emit_insn (gen_store_word<mode> (high, operands[1], const1_rtx)); @@ -4573,7 +4573,7 @@ ;; value in the low word. (define_insn "mthc1<mode>" [(set (match_operand:SPLITF 0 "register_operand" "=f") - (unspec:SPLITF [(match_operand:<HALFMODE> 1 "general_operand" "dJ") + (unspec:SPLITF [(match_operand:<HALFMODE> 1 "reg_or_0_operand" "dJ") (match_operand:SPLITF 2 "register_operand" "0")] UNSPEC_MTHC1))] "TARGET_HARD_FLOAT && ISA_HAS_MXHC1" |