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authorXi Ruoyao <xry111@mengyan1223.wang>2021-06-18 20:11:42 +0800
committerXi Ruoyao <xry111@mengyan1223.wang>2021-07-09 14:25:06 +0800
commit82625a42e652d52fc6bbe6070f8d0589d5e0c8ad (patch)
tree3852a5b9823e945a1a8ed62d1d112c3d36757a16 /gcc/config/mips
parent062c762ef264dca89d01ebca2ef023ea91f31d50 (diff)
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mips: check MSA support for vector modes [PR100760,PR100761,PR100762]
Check if the vector mode is really supported by MSA in certain cases, instead of testing ISA_HAS_MSA. Simply testing ISA_HAS_MSA can cause ICE when MSA is enabled besides other MIPS SIMD extensions (notably, Loongson MMI). gcc/ PR target/100760 PR target/100761 PR target/100762 * config/mips/mips.c (mips_const_insns): Use MSA_SUPPORTED_MODE_P instead of ISA_HAS_MSA. (mips_expand_vec_unpack): Likewise. (mips_expand_vector_init): Likewise. gcc/testsuite/ PR target/100760 PR target/100761 PR target/100762 * gcc.target/mips/pr100760.c: New test. * gcc.target/mips/pr100761.c: New test. * gcc.target/mips/pr100762.c: New test.
Diffstat (limited to 'gcc/config/mips')
-rw-r--r--gcc/config/mips/mips.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 1f1475c..00a8eef 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -2879,7 +2879,7 @@ mips_const_insns (rtx x)
return mips_build_integer (codes, INTVAL (x));
case CONST_VECTOR:
- if (ISA_HAS_MSA
+ if (MSA_SUPPORTED_MODE_P (GET_MODE (x))
&& mips_const_vector_same_int_p (x, GET_MODE (x), -512, 511))
return 1;
/* Fall through. */
@@ -21732,7 +21732,7 @@ mips_expand_vec_unpack (rtx operands[2], bool unsigned_p, bool high_p)
rtx (*cmpFunc) (rtx, rtx, rtx);
rtx tmp, dest, zero;
- if (ISA_HAS_MSA)
+ if (MSA_SUPPORTED_MODE_P (imode))
{
switch (imode)
{
@@ -21994,7 +21994,7 @@ mips_expand_vector_init (rtx target, rtx vals)
all_same = false;
}
- if (ISA_HAS_MSA)
+ if (MSA_SUPPORTED_MODE_P (vmode))
{
if (all_same)
{