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author | Ju-Zhe Zhong <juzhe.zhong@rivai.ai> | 2022-10-24 09:39:16 +0800 |
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committer | Kito Cheng <kito.cheng@sifive.com> | 2022-10-24 10:19:29 +0800 |
commit | 65908ac84b840ded3331e000d303d0a5b4b426c8 (patch) | |
tree | b2cf6d9b3133b3cb40db6b4731289c0c426fca19 /gcc/config/mips | |
parent | 00716b776200c2de6813ce706d2757eec4cb2735 (diff) | |
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RISC-V: Fix REG_CLASS_CONTENTS.
Include V_REGS for ALL_REGS.
gcc/ChangeLog:
* config/riscv/riscv.h (REG_CLASS_CONTENTS): Fix ALL_REGS.
Diffstat (limited to 'gcc/config/mips')
0 files changed, 0 insertions, 0 deletions