Fix some MIPS warnings

From-SVN: r40556

3 files changed, 29 insertions, 19 deletions

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 8467c88..23a05bc 100644
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -6452,12 +6452,13 @@ save_restore_insns (store_p, large_reg, large_offset, file)
 		  && GET_MODE (base_reg_rtx) == SImode)
 		{
 		  insn = emit_move_insn (base_reg_rtx,
-					 GEN_INT (gp_offset & 0xffff0000));
+					 GEN_INT (gp_offset & BITMASK_UPPER16));
 		  if (store_p)
 		    RTX_FRAME_RELATED_P (insn) = 1;
 		  insn
 		    = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
-					     GEN_INT (gp_offset & 0x0000ffff)));
+					     GEN_INT (gp_offset
+						      & BITMASK_LOWER16)));
 		  if (store_p)
 		    RTX_FRAME_RELATED_P (insn) = 1;
 		}
@@ -6671,11 +6672,12 @@ save_restore_insns (store_p, large_reg, large_offset, file)
 		  && GET_MODE (base_reg_rtx) == SImode)
 		{
 		  insn = emit_move_insn (base_reg_rtx,
-					 GEN_INT (fp_offset & 0xffff0000));
+					 GEN_INT (fp_offset & BITMASK_UPPER16));
 		  if (store_p)
 		    RTX_FRAME_RELATED_P (insn) = 1;
 		  insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
-						GEN_INT (fp_offset & 0x0000ffff)));
+						GEN_INT (fp_offset
+							 & BITMASK_LOWER16)));
 		  if (store_p)
 		    RTX_FRAME_RELATED_P (insn) = 1;
 		}
@@ -7223,10 +7225,11 @@ mips_expand_prologue ()
 		  && GET_MODE (tmp_rtx) == SImode)
 		{
 		  insn = emit_move_insn (tmp_rtx,
-					 GEN_INT (tsize & 0xffff0000));
+					 GEN_INT (tsize & BITMASK_UPPER16));
 		  RTX_FRAME_RELATED_P (insn) = 1;
 		  insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx,
-						GEN_INT (tsize & 0x0000ffff)));
+						GEN_INT (tsize
+							 & BITMASK_LOWER16)));
 		  RTX_FRAME_RELATED_P (insn) = 1;
 		}
 	      else
@@ -7342,7 +7345,7 @@ mips_expand_prologue ()
 /* Do any necessary cleanup after a function to restore stack, frame,
    and regs. */
 
-#define RA_MASK 0x80000000L	/* 1 << 31 */
+#define RA_MASK BITMASK_HIGH	/* 1 << 31 */
 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
 
 void
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 1510ecc..cdd0009 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -179,6 +179,13 @@ extern void		sbss_section PARAMS ((void));
 #define HALF_PIC_FINISH(STREAM)
 #endif
 
+/* Macros to silence warnings about numbers being signed in traditional
+   C and unsigned in ISO C when compiled on 32-bit hosts.  */
+
+#define BITMASK_HIGH	(((unsigned long)1) << 31)	/* 0x80000000 */
+#define BITMASK_UPPER16	((unsigned long)0xffff << 16)	/* 0xffff0000 */
+#define BITMASK_LOWER16	((unsigned long)0xffff)		/* 0x0000ffff */
+
 
 /* Run-time compilation parameters selecting different hardware subsets.  */
 
diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md
index 1f343f5..ceb4f6a 100644
--- a/gcc/config/mips/mips.md
+++ b/gcc/config/mips/mips.md
@@ -2277,7 +2277,7 @@
 			       copy_to_mode_reg (SImode, GEN_INT (-1)),
 			       GEN_INT (0x6)));
       emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (SImode, GEN_INT (0x80000000)),
+			       copy_to_mode_reg (SImode, GEN_INT (BITMASK_HIGH)),
 			       GEN_INT (0x6)));
     }
   
@@ -2324,7 +2324,7 @@
 			       copy_to_mode_reg (DImode, GEN_INT (-1)),
 			       GEN_INT (0x6)));
       emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (DImode, GEN_INT (0x80000000)),
+			       copy_to_mode_reg (DImode, GEN_INT (BITMASK_HIGH)),
 			       GEN_INT (0x6)));
     }
   
@@ -2535,7 +2535,7 @@
 			       copy_to_mode_reg (SImode, GEN_INT (-1)),
 			       GEN_INT (0x6)));
       emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (SImode, GEN_INT (0x80000000)),
+			       copy_to_mode_reg (SImode, GEN_INT (BITMASK_HIGH)),
 			       GEN_INT (0x6)));
     }
   
@@ -2575,7 +2575,7 @@
 			       copy_to_mode_reg (DImode, GEN_INT (-1)),
 			       GEN_INT (0x6)));
       emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (DImode, GEN_INT (0x80000000)),
+			       copy_to_mode_reg (DImode, GEN_INT (BITMASK_HIGH)),
 			       GEN_INT (0x6)));
     }
   
@@ -2615,7 +2615,7 @@
 			       copy_to_mode_reg (SImode, GEN_INT (-1)),
 			       GEN_INT (0x6)));
       emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (SImode, GEN_INT (0x80000000)),
+			       copy_to_mode_reg (SImode, GEN_INT (BITMASK_HIGH)),
 			       GEN_INT (0x6)));
     }
   
@@ -2655,7 +2655,7 @@
 			       copy_to_mode_reg (DImode, GEN_INT (-1)),
 			       GEN_INT (0x6)));
       emit_insn (gen_div_trap (operands[2],
-			       copy_to_mode_reg (DImode, GEN_INT (0x80000000)),
+			       copy_to_mode_reg (DImode, GEN_INT (BITMASK_HIGH)),
 			       GEN_INT (0x6)));
     }
   
@@ -4319,7 +4319,7 @@ move\\t%0,%z4\\n\\
 
       emit_label (label1);
       emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
-      emit_move_insn (reg3, GEN_INT (0x80000000));
+      emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
 
       emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
       emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
@@ -4362,7 +4362,7 @@ move\\t%0,%z4\\n\\
 
       emit_label (label1);
       emit_move_insn (reg2, gen_rtx_MINUS (DFmode, operands[1], reg1));
-      emit_move_insn (reg3, GEN_INT (0x80000000));
+      emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
       emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
 
       emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
@@ -4406,7 +4406,7 @@ move\\t%0,%z4\\n\\
 
       emit_label (label1);
       emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
-      emit_move_insn (reg3, GEN_INT (0x80000000));
+      emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
 
       emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
       emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
@@ -4449,7 +4449,7 @@ move\\t%0,%z4\\n\\
 
       emit_label (label1);
       emit_move_insn (reg2, gen_rtx_MINUS (SFmode, operands[1], reg1));
-      emit_move_insn (reg3, GEN_INT (0x80000000));
+      emit_move_insn (reg3, GEN_INT (BITMASK_HIGH));
       emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
 
       emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
@@ -5179,8 +5179,8 @@ move\\t%0,%z4\\n\\
 		(match_dup 3)))]
   "
 {
-  operands[2] = GEN_INT (INTVAL (operands[1]) & 0xffff0000);
-  operands[3] = GEN_INT (INTVAL (operands[1]) & 0x0000ffff);
+  operands[2] = GEN_INT (INTVAL (operands[1]) & BITMASK_UPPER16);
+  operands[3] = GEN_INT (INTVAL (operands[1]) & BITMASK_LOWER16);
 }")
 
 ;; Unlike most other insns, the move insns can't be split with