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author | Richard Sandiford <rdsandiford@googlemail.com> | 2008-12-02 22:30:57 +0000 |
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committer | Richard Sandiford <rsandifo@gcc.gnu.org> | 2008-12-02 22:30:57 +0000 |
commit | 0767b03f5e572d1b80604ce01090d9fc0ad406d3 (patch) | |
tree | e51bf5a52c02090b228c985914765115b76f7aa8 /gcc/config/mips | |
parent | c1af059c2c372c462d2e66d428207be3b59233f3 (diff) | |
download | gcc-0767b03f5e572d1b80604ce01090d9fc0ad406d3.zip gcc-0767b03f5e572d1b80604ce01090d9fc0ad406d3.tar.gz gcc-0767b03f5e572d1b80604ce01090d9fc0ad406d3.tar.bz2 |
mips.c (mips_expand_builtin): Fix the mode of the error return value.
gcc/
* config/mips/mips.c (mips_expand_builtin): Fix the mode of the
error return value.
* config/mips/mips.md (IMOVE32): New mode iterator.
(movsi): Generalize with IMOVE32.
(*movsi_internal): Likewise.
(*mov<mode>_mips16): Likewise, and its define_splits.
(*lwxs): Likewise.
From-SVN: r142375
Diffstat (limited to 'gcc/config/mips')
-rw-r--r-- | gcc/config/mips/mips.c | 5 | ||||
-rw-r--r-- | gcc/config/mips/mips.md | 60 |
2 files changed, 39 insertions, 26 deletions
diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index c7b3c06..b73b022 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -11923,8 +11923,7 @@ mips_expand_builtin_bposge (enum mips_builtin_type builtin_type, rtx target) static rtx mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, - enum machine_mode mode ATTRIBUTE_UNUSED, - int ignore ATTRIBUTE_UNUSED) + enum machine_mode mode, int ignore) { tree fndecl; unsigned int fcode, avail; @@ -11940,7 +11939,7 @@ mips_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, { error ("built-in function %qs not supported for MIPS16", IDENTIFIER_POINTER (DECL_NAME (fndecl))); - return const0_rtx; + return ignore ? const0_rtx : CONST0_RTX (mode); } switch (d->builtin_type) { diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index 21b76c5..698d57c 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -644,6 +644,18 @@ (define_mode_iterator MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT && !TARGET_LOONGSON_2EF")]) +;; 32-bit integer moves for which we provide move patterns. +(define_mode_iterator IMOVE32 + [SI + (V2HI "TARGET_DSP") + (V4QI "TARGET_DSP") + (V2HQ "TARGET_DSP") + (V2UHQ "TARGET_DSP") + (V2HA "TARGET_DSP") + (V2UHA "TARGET_DSP") + (V4QQ "TARGET_DSP") + (V4UQQ "TARGET_DSP")]) + ;; 64-bit modes for which we provide move patterns. (define_mode_iterator MOVE64 [DI DF @@ -3936,34 +3948,34 @@ ;; different predicates, because register spilling and other parts of ;; the compiler, have memoized the insn number already. -(define_expand "movsi" - [(set (match_operand:SI 0 "") - (match_operand:SI 1 ""))] +(define_expand "mov<mode>" + [(set (match_operand:IMOVE32 0 "") + (match_operand:IMOVE32 1 ""))] "" { - if (mips_legitimize_move (SImode, operands[0], operands[1])) + if (mips_legitimize_move (<MODE>mode, operands[0], operands[1])) DONE; }) ;; The difference between these two is whether or not ints are allowed ;; in FP registers (off by default, use -mdebugh to enable). -(define_insn "*movsi_internal" - [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m") - (match_operand:SI 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] +(define_insn "*mov<mode>_internal" + [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,d,e,d,m,*f,*f,*d,*m,*d,*z,*a,*d,*B*C*D,*B*C*D,*d,*m") + (match_operand:IMOVE32 1 "move_operand" "d,U,T,m,dJ,*d*J,*m,*f,*f,*z,*d,*J*d,*a,*d,*m,*B*C*D,*B*C*D"))] "!TARGET_MIPS16 - && (register_operand (operands[0], SImode) - || reg_or_0_operand (operands[1], SImode))" + && (register_operand (operands[0], <MODE>mode) + || reg_or_0_operand (operands[1], <MODE>mode))" { return mips_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,const,const,load,store,mtc,fpload,mfc,fpstore,mfc,mtc,mthilo,mfhilo,mtc,fpload,mfc,fpstore") (set_attr "mode" "SI")]) -(define_insn "*movsi_mips16" - [(set (match_operand:SI 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d") - (match_operand:SI 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))] +(define_insn "*mov<mode>_mips16" + [(set (match_operand:IMOVE32 0 "nonimmediate_operand" "=d,y,d,d,d,d,d,d,m,*d") + (match_operand:IMOVE32 1 "move_operand" "d,d,y,K,N,U,kf,m,d,*a"))] "TARGET_MIPS16 - && (register_operand (operands[0], SImode) - || register_operand (operands[1], SImode))" + && (register_operand (operands[0], <MODE>mode) + || register_operand (operands[1], <MODE>mode))" { return mips_output_move (operands[0], operands[1]); } [(set_attr "move_type" "move,move,move,const,constN,const,loadpool,load,store,mfhilo") (set_attr "mode" "SI")]) @@ -3973,9 +3985,9 @@ ;; load are 2 2 byte instructions. (define_split - [(set (match_operand:SI 0 "d_operand") - (mem:SI (plus:SI (match_dup 0) - (match_operand:SI 1 "const_int_operand"))))] + [(set (match_operand:IMOVE32 0 "d_operand") + (mem:IMOVE32 (plus:SI (match_dup 0) + (match_operand:SI 1 "const_int_operand"))))] "TARGET_MIPS16 && reload_completed && !TARGET_DEBUG_D_MODE && ((INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -0x80) @@ -3984,8 +3996,8 @@ || (INTVAL (operands[1]) >= 0 && INTVAL (operands[1]) < 32 * 4 && (INTVAL (operands[1]) & 3) != 0))" - [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1))) - (set (match_dup 0) (mem:SI (plus:SI (match_dup 0) (match_dup 2))))] + [(set (match_dup 3) (plus:SI (match_dup 0) (match_dup 1))) + (set (match_dup 0) (mem:IMOVE32 (plus:SI (match_dup 3) (match_dup 2))))] { HOST_WIDE_INT val = INTVAL (operands[1]); @@ -4005,6 +4017,7 @@ operands[1] = GEN_INT (off); operands[2] = GEN_INT (val - off); } + operands[3] = gen_rtx_REG (SImode, REGNO (operands[0])); }) ;; On the mips16, we can split a load of certain constants into a load @@ -4109,10 +4122,11 @@ ;; address expression, not shift. (define_insn "*lwxs" - [(set (match_operand:SI 0 "register_operand" "=d") - (mem:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") - (const_int 4)) - (match_operand:SI 2 "register_operand" "d"))))] + [(set (match_operand:IMOVE32 0 "register_operand" "=d") + (mem:IMOVE32 + (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "d") + (const_int 4)) + (match_operand:SI 2 "register_operand" "d"))))] "ISA_HAS_LWXS" "lwxs\t%0,%1(%2)" [(set_attr "type" "load") |