Fix up MIPS16 hard float and add support for complex.

2007-05-23  Sandra Loosemore  <sandra@codesourcery.com>
	    Nigel Stephens  <nigel@mips.com>
	    Richard Sandiford  <richard@codesourcery.com>

	gcc/
	Fix up MIPS16 hard float and add support for complex.

	* config/mips/mips.h (TARGET_HARD_FLOAT_ABI): New.
	(TARGET_SOFT_FLOAT_ABI): New.
	(TARGET_CPU_CPP_BUILTINS): Define __mips_hard_float and
	__mips_soft_float to reflect the ABI in use, not whether the
	FPU is directly accessible (e.g., in MIPS16 mode).
	(UNITS_PER_HWFPVALUE): Use TARGET_SOFT_FLOAT_ABI.
	(UNITS_PER_FPVALUE): Likewise.

	* config/mips/mips.c (mips_expand_call): Remove redundant
	TARGET_MIPS16 check.
	(mips_arg_regno): New.
	(function_arg_advance): When setting bits in cum->fp_code for
	MIPS16, don't subtract 1 from cum->arg_number, since it is now
	zero-based.
	(function_arg): Use mips_arg_regno.
	(mips_return_mode_in_fpr_p): New.
	(mips16_call_stub_mode_suffix): New.
	(mips16_cfun_returns_in_fpr_p): New.
	(mips_save_reg_p): Use mips16_cfun_returns_in_fpr_p.
	(mips_output_function_prologue): Test mips16_hard_float, not
	!TARGET_SOFT_FLOAT, to decide when a function stub is required.
	(mips_expand_epilogue): Call MIPS16 helper routines to copy
	return value into a floating-point register.
	(mips_can_use_return_insn): Use mips16_cfun_returns_in_fpr_p.
	(mips_function_value): Rewrite to use mips_return_mode_in_fpr_p.
	(mips16_fp_args): Handle MIPS32r2 ISA which supports
	TARGET_FLOAT64, and use mfhc1/mthc1 to copy the most significant
	word of double arguments from or to the high bits of 64-bit
	floating point registers.
	(build_mips16_function_stub): Fill in DECL_RESULT for stubdecl.
	(mips16_fpret_double): New helper function.
	(build_mips16_call_stub): Use mips16_return_mode_in_fpr_p.  Add
	support for complex modes.  Fill in DECL_RESULT for stubdecl.
	(mips_init_libfuncs): Remove redundant TARGET_MIPS16 check.

	* config/mips/mips16.S 
	(RET, ARG1, ARG2): New.
	(MERGE_GPRf, MERGE_GPRt): New.
	(DELAYt, DELAYf): New.
	(MOVE_SF_BYTE0, MOVE_SI_BYTE0): New.
	(MOVE_SF_BYTE4, MOVE_SF_BYTE8): New.
	(MOVE_DF_BYTE0, MOVE_DF_BYTE8): New.
	(MOVE_SF_RET, MOVE_SC_RET, MOVE_DF_RET, MOVE_DC_RET, MOVE_SI_RET): New.
	(SFOP): Renamed to...
	(OPSF3): This, and macro-ified.  Updated all uses.
	(SFOP2): Renamed to...
	(OPSF2): This, and macro-ified.  Updated all uses.
	(SFCMP): Renamed to...
	(CMPSF): This, and macro-ified.  Updated all uses.
	(SFREVCMP): Renamed to...
	(REVCMPSF): This, and macro-ified.  Updated all uses.
	(__mips16_floatsisf, __mips16_fix_truncsfsi): Macro-ified.
	(LDDBL1, LDDBL2, RETDBL): Deleted.
	(DFOP): Renamed to...
	(OPDF3): This, and macro-ified.  Updated all uses.
	(DFOP2): Renamed to...
	(OPDF2): This, and macro-ified.  Updated all uses.
	(__mips16_extendsfdf2, __mips16_truncdfsf2): Macro-ified.
	(DFCMP): Renamed to...
	(CMPDF): This, and macro-ified.  Updated all uses.
	(DFREVCMP): Renamed to...
	(REVCMPDF): This, and macro-ified.  Updated all uses.
	(__mips16_floatsidf, __mips16_fix_truncdfsi): Macro-ified.
	(RET_FUNCTION): New.
	(__mips16_ret_sf, __mips16_ret_df): Macro-ified.
	(__mips16_ret_sc, __mips16_ret_dc): New.
	(STUB_ARGS_0, STUB_ARGS_1, STUB_ARGS_5, STUB_ARGS_9, STUB_ARGS_2,
	STUB_ARGS_6, STUB_ARGS_10): New.
	(CALL_STUB_NO_RET): New.
	(__mips16_call_stub_1): Macro-ified.
	(__mips16_call_stub_5): Macro-ified.
	(__mips16_call_stub_2): Macro-ified.
	(__mips16_call_stub_6): Macro-ified.
	(__mips16_call_stub_9): Macro-ified.
	(__mips16_call_stub_10): Macro-ified.
	(CALL_STUB_RET): New.
	(__mips16_call_stub_sf_0): Macro-ified.
	(__mips16_call_stub_sf_1): Macro-ified.
	(__mips16_call_stub_sf_5): Macro-ified.
	(__mips16_call_stub_sf_2): Macro-ified.
	(__mips16_call_stub_sf_6): Macro-ified.
	(__mips16_call_stub_sf_9): Macro-ified.
	(__mips16_call_stub_sf_10): Macro-ified.
	(__mips16_call_stub_df_0): Macro-ified.
	(__mips16_call_stub_df_1): Macro-ified.
	(__mips16_call_stub_df_5): Macro-ified.
	(__mips16_call_stub_df_2): Macro-ified.
	(__mips16_call_stub_df_6): Macro-ified.
	(__mips16_call_stub_df_9): Macro-ified.
	(__mips16_call_stub_df_10): Macro-ified.
	(__mips16_call_stub_sc_0): New.
	(__mips16_call_stub_sc_1): New.
	(__mips16_call_stub_sc_5): New.
	(__mips16_call_stub_sc_2): New.
	(__mips16_call_stub_sc_6): New.
	(__mips16_call_stub_sc_9): New.
	(__mips16_call_stub_sc_10): New.
	(__mips16_call_stub_dc_0): New.
	(__mips16_call_stub_dc_1): New.
	(__mips16_call_stub_dc_5): New.
	(__mips16_call_stub_dc_2): New.
	(__mips16_call_stub_dc_6): New.
	(__mips16_call_stub_dc_9): New.
	(__mips16_call_stub_dc_10): New.
	
	* config/mips/t-elf (LIB1ASMFUNCS): Add MIPS16 floating-point stubs.
	* config/mips/t-isa3264 (LIB1ASMFUNCS): Likewise.
	* config/mips/t-r2900 (LIB1ASMFUNCS): Likewise.

	gcc/testsuite/
	* gcc.target/mips/inter/mips16_stubs_1_main.c: New.
	* gcc.target/mips/inter/mips16_stubs_1_x.c: New.
	* gcc.target/mips/inter/mips16_stubs_1_y.c: New.
	* gcc.target/mips/inter/mips16-inter.exp: New.


Co-Authored-By: Nigel Stephens <nigel@mips.com>
Co-Authored-By: Richard Sandiford <richard@codesourcery.com>

From-SVN: r124999

1 files changed, 6 insertions, 1 deletions

diff --git a/gcc/config/mips/t-r3900 b/gcc/config/mips/t-r3900
index 3bc8c47..1245598 100644
--- a/gcc/config/mips/t-r3900
+++ b/gcc/config/mips/t-r3900
@@ -7,11 +7,16 @@ LIB1ASMFUNCS = _m16addsf3 _m16subsf3 _m16mulsf3 _m16divsf3 \
 	_m16eqdf2 _m16nedf2 _m16gtdf2 _m16gedf2 _m16ledf2 _m16ltdf2 \
 	_m16fltsidf _m16fix_truncdfsi \
 	_m16retsf _m16retdf \
+	_m16retsc _m16retdc \
 	_m16stub1 _m16stub2 _m16stub5 _m16stub6 _m16stub9 _m16stub10 \
 	_m16stubsf0 _m16stubsf1 _m16stubsf2 _m16stubsf5 _m16stubsf6 \
 	_m16stubsf9 _m16stubsf10 \
 	_m16stubdf0 _m16stubdf1 _m16stubdf2 _m16stubdf5 _m16stubdf6 \
-	_m16stubdf9 _m16stubdf10
+	_m16stubdf9 _m16stubdf10 \
+	_m16stubsc0 _m16stubsc1 _m16stubsc2 _m16stubsc5 _m16stubsc6 \
+	_m16stubsc9 _m16stubsc10 \
+	_m16stubdc0 _m16stubdc1 _m16stubdc2 _m16stubdc5 _m16stubdc6 \
+	_m16stubdc9 _m16stubdc10
 
 # We must build libgcc2.a with -G 0, in case the user wants to link
 # without the $gp register.