diff options
| author | Chenghua Xu <paul.hua.gm@gmail.com> | 2018-11-07 08:42:59 +0000 |
|---|---|---|
| committer | Chenghua Xu <paulhua@gcc.gnu.org> | 2018-11-07 08:42:59 +0000 |
| commit | d6319811c1af2f2a36a83d2079eb986154060e60 (patch) | |
| tree | 3f722255f7e301897a38a5bbf0aa031b62f652fc /gcc/config/mips/mips.h | |
| parent | 375899d9e47d03f3f2fe6aa6c854ddc855f94d76 (diff) | |
| download | gcc-d6319811c1af2f2a36a83d2079eb986154060e60.zip gcc-d6319811c1af2f2a36a83d2079eb986154060e60.tar.gz gcc-d6319811c1af2f2a36a83d2079eb986154060e60.tar.bz2 | |
Add support for Loongson EXT2 instructions.
gcc/
* config/mips/mips-protos.h
(mips_loongson_ext2_prefetch_cookie): New prototype.
* config/mips/mips.c (mips_loongson_ext2_prefetch_cookie): New.
(mips_option_override): Enable TARGET_LOONGSON_EXT when
TARGET_LOONGSON_EXT2 is true.
* config/mips/mips.h (TARGET_CPU_CPP_BUILTINS): Define
__mips_loongson_ext2, __mips_loongson_ext_rev=2.
(ISA_HAS_CTZ_CTO): New, true if TARGET_LOONGSON_EXT2.
(ISA_HAS_PREFETCH): Include TARGET_LOONGSON_EXT and
TARGET_LOONGSON_EXT2.
(ASM_SPEC): Add mloongson-ext2 and mno-loongson-ext2.
(define_insn "ctz<mode>2"): New insn pattern.
(define_insn "prefetch"): Include TARGET_LOONGSON_EXT2.
(define_insn "prefetch_indexed_<mode>"): Include
TARGET_LOONGSON_EXT and TARGET_LOONGSON_EXT2.
* config/mips/mips.opt (-mloongson-ext2): Add option.
* gcc/doc/invoke.texi (-mloongson-ext2): Document.
gcc/testsuite/
* gcc.target/mips/loongson-ctz.c: New test.
* gcc.target/mips/loongson-dctz.c: Likewise.
* gcc.target/mips/mips.exp (mips_option_groups): Add
-mloongson-ext2 option.
From-SVN: r265864
Diffstat (limited to 'gcc/config/mips/mips.h')
| -rw-r--r-- | gcc/config/mips/mips.h | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 7237c8d..beeb4bc 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -600,6 +600,13 @@ struct mips_cpu_info { if (TARGET_LOONGSON_EXT) \ { \ builtin_define ("__mips_loongson_ext"); \ + if (TARGET_LOONGSON_EXT2) \ + { \ + builtin_define ("__mips_loongson_ext2"); \ + builtin_define ("__mips_loongson_ext_rev=2"); \ + } \ + else \ + builtin_define ("__mips_loongson_ext_rev=1"); \ } \ \ /* Historical Octeon macro. */ \ @@ -1134,6 +1141,9 @@ struct mips_cpu_info { /* ISA has count leading zeroes/ones instruction (not implemented). */ #define ISA_HAS_CLZ_CLO (mips_isa_rev >= 1 && !TARGET_MIPS16) +/* ISA has count tailing zeroes/ones instruction. */ +#define ISA_HAS_CTZ_CTO (TARGET_LOONGSON_EXT2) + /* ISA has three operand multiply instructions that put the high part in an accumulator: mulhi or mulhiu. */ #define ISA_HAS_MULHI ((TARGET_MIPS5400 \ @@ -1195,7 +1205,9 @@ struct mips_cpu_info { 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT. (prefx is a cop1x instruction, so can only be used if FP is enabled.) */ -#define ISA_HAS_PREFETCHX ISA_HAS_FP4 +#define ISA_HAS_PREFETCHX (ISA_HAS_FP4 \ + || TARGET_LOONGSON_EXT \ + || TARGET_LOONGSON_EXT2) /* True if trunc.w.s and trunc.w.d are real (not synthetic) instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d @@ -1379,6 +1391,7 @@ struct mips_cpu_info { %{mmsa} %{mno-msa} \ %{mloongson-mmi} %{mno-loongson-mmi} \ %{mloongson-ext} %{mno-loongson-ext} \ +%{mloongson-ext2} %{mno-loongson-ext2} \ %{msmartmips} %{mno-smartmips} \ %{mmt} %{mno-mt} \ %{mfix-rm7000} %{mno-fix-rm7000} \ |