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| author | Matthew Fortune <matthew.fortune@mips.com> | 2018-06-13 20:40:28 +0000 |
|---|---|---|
| committer | Robert Suchanek <rts@gcc.gnu.org> | 2018-06-13 20:40:28 +0000 |
| commit | 30c0ee9ca68e62a066f2653da11c50f708666857 (patch) | |
| tree | eb64925dcae8e0e75f32d31b1b8b35f896611627 /gcc/config/mips/mips.h | |
| parent | 1df5fce42a295ae8cb34c6a4aae30814679b0b59 (diff) | |
| download | gcc-30c0ee9ca68e62a066f2653da11c50f708666857.zip gcc-30c0ee9ca68e62a066f2653da11c50f708666857.tar.gz gcc-30c0ee9ca68e62a066f2653da11c50f708666857.tar.bz2 | |
MIPS: Add support for P6600.
gcc/ChangeLog:
2018-06-13 Matthew Fortune <matthew.fortune@mips.com>
Prachi Godbole <prachi.godbole@imgtec.com>
* config/mips/mips-cpus.def: Define P6600.
* config/mips/mips-tables.opt: Regenerate.
* config/mips/mips.c (mips_ucbranch_type): New enum.
(mips_rtx_cost_data): Add support for P6600.
(mips_issue_rate): Likewise.
(mips_multipass_dfa_lookahead): Likewise.
(mips_avoid_hazard): Likewise.
(mips_reorg_process_insns): Likewise.
(mips_classify_branch_p6600): New function.
* config/mips/mips.h (TUNE_P6600): New define.
(MIPS_ISA_LEVEL_SPEC): Infer mips64r6 from p6600.
(ENABLE_LD_ST_PAIRS): Enable load/store bonding for p6600.
* config/mips/mips.md: Include p6600.md.
(processor): Add p6600.
* config/mips/p6600.md: New file.
* doc/invoke.texi: Add p6600 to supported architectures.
Co-Authored-By: Prachi Godbole <prachi.godbole@imgtec.com>
From-SVN: r261570
Diffstat (limited to 'gcc/config/mips/mips.h')
| -rw-r--r-- | gcc/config/mips/mips.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 705434e..61c5ae2 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -317,6 +317,7 @@ struct mips_cpu_info { || mips_tune == PROCESSOR_SB1A) #define TUNE_P5600 (mips_tune == PROCESSOR_P5600) #define TUNE_I6400 (mips_tune == PROCESSOR_I6400) +#define TUNE_P6600 (mips_tune == PROCESSOR_P6600) /* Whether vector modes and intrinsics for ST Microelectronics Loongson-2E/2F processors should be enabled. In o32 pairs of @@ -782,7 +783,7 @@ struct mips_cpu_info { %{march=mips64r2|march=loongson3a|march=octeon|march=xlp: -mips64r2} \ %{march=mips64r3: -mips64r3} \ %{march=mips64r5: -mips64r5} \ - %{march=mips64r6|march=i6400|march=i6500: -mips64r6}}" + %{march=mips64r6|march=i6400|march=i6500|march=p6600: -mips64r6}}" /* A spec that injects the default multilib ISA if no architecture is specified. */ @@ -3403,5 +3404,6 @@ struct GTY(()) machine_function { performance can be degraded for those targets. Hence, do not bond for micromips or fix_24k. */ #define ENABLE_LD_ST_PAIRS \ - (TARGET_LOAD_STORE_PAIRS && (TUNE_P5600 || TUNE_I6400) \ + (TARGET_LOAD_STORE_PAIRS \ + && (TUNE_P5600 || TUNE_I6400 || TUNE_P6600) \ && !TARGET_MICROMIPS && !TARGET_FIX_24K) |