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authorJie Mei <jie.mei@oss.cipunited.com>2024-04-28 16:57:31 +0800
committerYunQiang Su <syq@gcc.gnu.org>2024-04-29 11:56:04 +0800
commit11c13111ac64a035d6c4ea6c118eff4ece7a9d9b (patch)
treeea255cf0f532fdaae78d0e6c9d4c7fb362f5729e /gcc/config/mips/mips.h
parentdeb69bfbb000339fbef316916cf6c46156c6af1b (diff)
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MIPS: Add MIN/MAX.fmt instructions support for MIPS R6
This patch adds the smin/smax RTL mode for the min/max.fmt instructions. Also, since the min/max.fmt instrucions applies to the IEEE 754-2008 "minNum" and "maxNum" operations, this patch also provides the new "fmin<mode>3" and "fmax<mode>3" modes. gcc/ChangeLog: * config/mips/i6400.md (i6400_fpu_minmax): New define_insn_reservation. * config/mips/mips.h (ISA_HAS_FMIN_FMAX): Define new macro. * config/mips/mips.md (UNSPEC_FMIN): New unspec. (UNSPEC_FMAX): Same as above. (type): Add fminmax. (smin<mode>3): Generates MIN.fmt instructions. (smax<mode>3): Generates MAX.fmt instructions. (fmin<mode>3): Generates MIN.fmt instructions. (fmax<mode>3): Generates MAX.fmt instructions. * config/mips/p6600.md (p6600_fpu_fabs): Include fminmax type. gcc/testsuite/ChangeLog: * gcc.target/mips/mips-minmax1.c: New test for MIPS R6. * gcc.target/mips/mips-minmax2.c: Same as above.
Diffstat (limited to 'gcc/config/mips/mips.h')
-rw-r--r--gcc/config/mips/mips.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index 616a275..9d96596 100644
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1262,6 +1262,8 @@ struct mips_cpu_info {
#define ISA_HAS_9BIT_DISPLACEMENT (mips_isa_rev >= 6 \
|| ISA_HAS_MIPS16E2)
+#define ISA_HAS_FMIN_FMAX (mips_isa_rev >= 6)
+
/* ISA has data indexed prefetch instructions. This controls use of
'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
(prefx is a cop1x instruction, so can only be used if FP is