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authorRichard Sandiford <rdsandiford@googlemail.com>2014-01-25 20:16:14 +0000
committerRichard Sandiford <rsandifo@gcc.gnu.org>2014-01-25 20:16:14 +0000
commit317a951fc75f1afb5e4fc25810722cf9044da7ed (patch)
tree61e1e082d8cd475a243a3d27fe8660aefe81dfd5 /gcc/config/mips/constraints.md
parent3abe9053ba83798e124f9efe9996e42a7d07a4e8 (diff)
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constraints.md (kl): Delete.
gcc/ * config/mips/constraints.md (kl): Delete. * config/mips/mips.md (divmod<mode>4, udivmod<mode>4): Turn into define expands, using... (divmod<mode>4_mips16, udivmod<mode>4_mips16): ...these new instructions for MIPS16. (*divmod<mode>4, *udivmod<mode>4): New patterns, taken from the non-MIPS16 version of the old divmod<mode>4 and udivmod<mode>4. From-SVN: r207079
Diffstat (limited to 'gcc/config/mips/constraints.md')
-rw-r--r--gcc/config/mips/constraints.md6
1 files changed, 0 insertions, 6 deletions
diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md
index 196b3e1..49e4895 100644
--- a/gcc/config/mips/constraints.md
+++ b/gcc/config/mips/constraints.md
@@ -92,12 +92,6 @@
;; but the DSP version allows any accumulator target.
(define_register_constraint "ka" "ISA_HAS_DSP_MULT ? ACC_REGS : MD_REGS")
-;; The register class to use for an allocatable division result.
-;; MIPS16 uses M16_REGS because LO is fixed.
-(define_register_constraint "kl"
- "TARGET_MIPS16 ? M16_REGS : TARGET_BIG_ENDIAN ? MD1_REG : MD0_REG"
- "@internal")
-
(define_constraint "kf"
"@internal"
(match_operand 0 "force_to_mem_operand"))