[MIPS] Update the ZC constraint.

gcc/

	* config/mips/constraints.md (ZC): Add support for R6 LL/SC
	offsets.
	(ZD): Update to use ISA_HAS_9BIT_DISPLACEMENT.
	* config/mips/mips.h (ISA_HAS_PREFETCH_9BIT): Rename to...
	(ISA_HAS_9BIT_DISPLACEMENT): ... this. New macro.
	* config/mips/sync.md (sync_compare_and_swap<mode>): Use ZC
	instead of ZR for the memory operand of LL/SC.
	(compare_and_swap_12, sync_add<mode>): Likewise.
	(sync_<optab>_12, sync_old_<optab>_12): Likewise.
	(sync_new_<optab>_12, sync_nand_12): Likewise.
	(sync_old_nand_12, sync_new_nand_12): Likewise.
	(sync_sub<mode>, sync_old_add<mode>): Likewise.
	(sync_old_sub<mode>, sync_new_add<mode>): Likewise.
	(sync_new_sub<mode>, sync_<optab><mode>): Likewise.
	(sync_old_<optab><mode>, sync_new_<optab><mode>"): Likewise.
	(sync_nand<mode>, sync_old_nand<mode>): Likewise.
	(sync_new_nand<mode>, sync_lock_test_and_set<mode>): Likewise.
	(test_and_set_12, atomic_compare_and_swap<mode>): Likewise.
	(atomic_exchange<mode>_llsc, atomic_fetch_add<mode>_llsc): Likewise.
	* doc/md.texi (ZC): Update description.

From-SVN: r219619

1 files changed, 7 insertions, 7 deletions

diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md
index c23dc47..7d1a8ba 100644
--- a/gcc/config/mips/constraints.md
+++ b/gcc/config/mips/constraints.md
@@ -309,23 +309,23 @@
    (match_operand 0 "low_bitmask_operand"))
 
 (define_memory_constraint "ZC"
-  "When compiling microMIPS code, this constraint matches a memory operand
-   whose address is formed from a base register and a 12-bit offset.  These
-   operands can be used for microMIPS instructions such as @code{ll} and
-   @code{sc}.  When not compiling for microMIPS code, @code{ZC} is
-   equivalent to @code{R}."
+  "A memory operand whose address is formed by a base register and offset
+   that is suitable for use in instructions with the same addressing mode
+   as @code{ll} and @code{sc}."
   (and (match_code "mem")
        (if_then_else
 	 (match_test "TARGET_MICROMIPS")
 	 (match_test "umips_12bit_offset_address_p (XEXP (op, 0), mode)")
-	 (match_test "mips_address_insns (XEXP (op, 0), mode, false)"))))
+	 (if_then_else (match_test "ISA_HAS_9BIT_DISPLACEMENT")
+	   (match_test "mips_9bit_offset_address_p (XEXP (op, 0), mode)")
+	   (match_test "mips_address_insns (XEXP (op, 0), mode, false)")))))
 
 (define_address_constraint "ZD"
   "An address suitable for a @code{prefetch} instruction, or for any other
    instruction with the same addressing mode as @code{prefetch}."
    (if_then_else (match_test "TARGET_MICROMIPS")
 		 (match_test "umips_12bit_offset_address_p (op, mode)")
-	  (if_then_else (match_test "ISA_HAS_PREFETCH_9BIT")
+	  (if_then_else (match_test "ISA_HAS_9BIT_DISPLACEMENT")
 			(match_test "mips_9bit_offset_address_p (op, mode)")
 			(match_test "mips_address_insns (op, mode, false)"))))