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author | Richard Sandiford <rsandifo@redhat.com> | 2004-06-30 17:27:54 +0000 |
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committer | Eric Christopher <echristo@gcc.gnu.org> | 2004-06-30 17:27:54 +0000 |
commit | b5674962f18be68ae4b22042b09fd251ccd09ed1 (patch) | |
tree | 73ff6cba0291db6bf79d9fcbfaaf713fe71786d9 /gcc/config/mips/3000.md | |
parent | 74fe2f96ca0834c247e3241eab98567de677cdc6 (diff) | |
download | gcc-b5674962f18be68ae4b22042b09fd251ccd09ed1.zip gcc-b5674962f18be68ae4b22042b09fd251ccd09ed1.tar.gz gcc-b5674962f18be68ae4b22042b09fd251ccd09ed1.tar.bz2 |
3000.md: Improve description.
2004-06-30 Richard Sandiford <rsandifo@redhat.com>
Eric Christopher <echristo@redhat.com>
* config/mips/3000.md: Improve description.
From-SVN: r83917
Diffstat (limited to 'gcc/config/mips/3000.md')
-rw-r--r-- | gcc/config/mips/3000.md | 81 |
1 files changed, 45 insertions, 36 deletions
diff --git a/gcc/config/mips/3000.md b/gcc/config/mips/3000.md index 9282597..8c9a0d6 100644 --- a/gcc/config/mips/3000.md +++ b/gcc/config/mips/3000.md @@ -2,68 +2,77 @@ ;; This is a special pipeline - this is also the default schedule and ;; so we need to schedule instructions that may not exist on the r2k/r3k. -;; Generic processor description that assumes that the only latencies are for -;; hazards or delay slots, otherwise everything is assumed to issue and execute -;; in one cycle. -(define_automaton "r3k") +(define_automaton "r3k_alu,r3k_imuldiv") -(define_cpu_unit "r3k_alu" "r3k") +(define_cpu_unit "r3k_alu" "r3k_alu") +(define_cpu_unit "r3k_imuldiv" "r3k_imuldiv") -(define_insn_reservation "r3k_generic_alu" 1 +(define_insn_reservation "r3k_generic" 1 (and (eq_attr "cpu" "r3000") - (eq_attr "type" "unknown,prefetch,prefetchx,condmove,mthilo,const,arith,shift,slt,clz,trap,fmove,fadd,fmadd,fabs,fneg,fcvt,fsqrt,frsqrt,multi,nop")) + (eq_attr "type" "unknown,prefetch,prefetchx,condmove,const,arith, + shift,slt,clz,trap,multi,nop")) "r3k_alu") -(define_insn_reservation "r3k_load_alu" 2 +(define_insn_reservation "r3k_load" 2 (and (eq_attr "cpu" "r3000") - (eq_attr "type" "load, fpload, fpidxload, xfer")) - "r3k_alu*2") + (eq_attr "type" "load,fpload,fpidxload,xfer")) + "r3k_alu") -(define_insn_reservation "r3k_call_alu" 2 +(define_insn_reservation "r3k_store" 1 (and (eq_attr "cpu" "r3000") - (eq_attr "type" "branch,jump,call")) - "r3k_alu*2") + (eq_attr "type" "store,fpstore,fpidxstore")) + "r3k_alu") -(define_insn_reservation "r3k_hilo_alu" 3 +(define_insn_reservation "r3k_branch" 1 (and (eq_attr "cpu" "r3000") - (eq_attr "type" "mfhilo")) - "r3k_alu*3") + (eq_attr "type" "branch,jump,call")) + "r3k_alu") -(define_insn_reservation "r3k_fcmp_alu" 2 +(define_insn_reservation "r3k_hilo" 1 (and (eq_attr "cpu" "r3000") - (eq_attr "type" "fcmp, fadd")) - "r3k_alu*2") + (eq_attr "type" "mfhilo,mthilo")) + "r3k_imuldiv*3") -(define_insn_reservation "r3k_imul_alu" 12 +(define_insn_reservation "r3k_imul" 12 (and (eq_attr "cpu" "r3000") - (eq_attr "type" "imul, imadd")) - "r3k_alu*12") + (eq_attr "type" "imul,imadd")) + "r3k_imuldiv*12") -(define_insn_reservation "r3k_idiv_alu" 35 +(define_insn_reservation "r3k_idiv" 35 (and (eq_attr "cpu" "r3000") (eq_attr "type" "idiv")) - "r3k_alu*35") + "r3k_imuldiv*35") + +(define_insn_reservation "r3k_fmove" 1 + (and (eq_attr "cpu" "r3000") + (eq_attr "type" "fabs,fneg,fmove,fcvt")) + "r3k_alu") -(define_insn_reservation "r3k_fmul_single_alu" 4 +(define_insn_reservation "r3k_fadd" 2 (and (eq_attr "cpu" "r3000") - (and (eq_attr "type" "fmul") + (eq_attr "type" "fcmp,fadd")) + "r3k_alu") + +(define_insn_reservation "r3k_fmul_single" 4 + (and (eq_attr "cpu" "r3000") + (and (eq_attr "type" "fmul,fmadd") (eq_attr "mode" "SF"))) - "r3k_alu*4") + "r3k_alu") -(define_insn_reservation "r3k_fmul_double_alu" 5 +(define_insn_reservation "r3k_fmul_double" 5 (and (eq_attr "cpu" "r3000") - (and (eq_attr "type" "fmul") + (and (eq_attr "type" "fmul,fmadd") (eq_attr "mode" "DF"))) - "r3k_alu*5") + "r3k_alu") -(define_insn_reservation "r3k_fdiv_single_alu" 12 +(define_insn_reservation "r3k_fdiv_single" 12 (and (eq_attr "cpu" "r3000") - (and (eq_attr "type" "fdiv") + (and (eq_attr "type" "fdiv,fsqrt,frsqrt") (eq_attr "mode" "SF"))) - "r3k_alu*12") + "r3k_alu") -(define_insn_reservation "r3k_fdiv_double_alu" 19 +(define_insn_reservation "r3k_fdiv_double" 19 (and (eq_attr "cpu" "r3000") - (and (eq_attr "type" "fdiv") + (and (eq_attr "type" "fdiv,fsqrt,frsqrt") (eq_attr "mode" "DF"))) - "r3k_alu*19") + "r3k_alu") |