diff options
| author | James E Wilson <wilson@specifixinc.com> | 2005-08-17 14:43:49 -0700 |
|---|---|---|
| committer | Jim Wilson <wilson@gcc.gnu.org> | 2005-08-17 14:43:49 -0700 |
| commit | 90e0c734fa7ee61bacefcbdccfa0c22dad59c579 (patch) | |
| tree | c8d27614713d44d1a41d9835b3c2b26a8cce3b7d /gcc/config/mcore | |
| parent | 97b51fd08ea84c07be2c7fea17210453eef46371 (diff) | |
| download | gcc-90e0c734fa7ee61bacefcbdccfa0c22dad59c579.zip gcc-90e0c734fa7ee61bacefcbdccfa0c22dad59c579.tar.gz gcc-90e0c734fa7ee61bacefcbdccfa0c22dad59c579.tar.bz2 | |
Fix misoptimization of mask and shift.
PR target/21684
* config/mcore/mcore.h (SHIFT_COUNT_TRUNCATED): Define to 0.
Co-Authored-By: Kevin Winchester <winchester@amirix.com>
From-SVN: r103228
Diffstat (limited to 'gcc/config/mcore')
| -rw-r--r-- | gcc/config/mcore/mcore.h | 10 |
1 files changed, 4 insertions, 6 deletions
diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h index f0afa88..d9960dc 100644 --- a/gcc/config/mcore/mcore.h +++ b/gcc/config/mcore/mcore.h @@ -820,12 +820,10 @@ extern const enum reg_class reg_class_from_letter[]; /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES -/* Immediate shift counts are truncated by the output routines (or was it - the assembler?). Shift counts in a register are truncated by ARM. Note - that the native compiler puts too large (> 32) immediate shift counts - into a register and shifts by the register, letting the ARM decide what - to do instead of doing that itself. */ -#define SHIFT_COUNT_TRUNCATED 1 +/* Shift counts are truncated to 6-bits (0 to 63) instead of the expected + 5-bits, so we can not define SHIFT_COUNT_TRUNCATED to true for this + target. */ +#define SHIFT_COUNT_TRUNCATED 0 /* All integers have the same format so truncation is easy. */ #define TRULY_NOOP_TRUNCATION(OUTPREC,INPREC) 1 |