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| author | Roger Sayle <roger@eyesopen.com> | 2003-06-14 21:47:45 +0000 |
|---|---|---|
| committer | Roger Sayle <sayle@gcc.gnu.org> | 2003-06-14 21:47:45 +0000 |
| commit | 06f31100d2a2eed8e93c7784f455b5925b72ee97 (patch) | |
| tree | fa9882a13a8acd24f7113752447301736a903e16 /gcc/config/mcore | |
| parent | b7a7058884e0671a712b73b6c85274200d40f4df (diff) | |
| download | gcc-06f31100d2a2eed8e93c7784f455b5925b72ee97.zip gcc-06f31100d2a2eed8e93c7784f455b5925b72ee97.tar.gz gcc-06f31100d2a2eed8e93c7784f455b5925b72ee97.tar.bz2 | |
rtl.h (STORE_FLAG_VALUE): Remove default definition from here.
* rtl.h (STORE_FLAG_VALUE): Remove default definition from here.
* defaults.h (STORE_FLAG_VALUE): Move default definition to here.
* doc/tm.texi (STORE_FLAG_VALUE): Document the default value.
* config/alpha/alpha.h (STORE_FLAG_VALUE): Remove definition.
* config/arc/arc.h (STORE_FLAG_VALUE): Likewise.
* config/arm/arm.h (STORE_FLAG_VALUE): Likewise.
* config/cris/cris.h (STORE_FLAG_VALUE): Likewise.
* config/i370/i370.h (STORE_FLAG_VALUE): Likewise.
* config/i386/i386.h (STORE_FLAG_VALUE): Likewise.
* config/i960/i960.h (STORE_FLAG_VALUE): Likewise.
* config/ia64/ia64.h (STORE_FLAG_VALUE): Likewise.
* config/ip2k/ip2k.h (STORE_FLAG_VALUE): Likewise.
* config/m32r/m32r.h (STORE_FLAG_VALUE): Likewise.
* config/mcore/mcore.h (STORE_FLAG_VALUE): Likewise.
* config/mips/mips.h (STORE_FLAG_VALUE): Likewise.
* config/mmix/mmix.h (STORE_FLAG_VALUE): Likewise.
* config/ns32k/ns32k.h (STORE_FLAG_VALUE): Likewise.
* config/pa/pa.h (STORE_FLAG_VALUE): Likewise.
* config/pdp11/pdp11.h (STORE_FLAG_VALUE): Likewise.
* config/sh/sh.h (STORE_FLAG_VALUE): Likewise.
* config/sparc/sparc.h (STORE_FLAG_VALUE): Likewise.
* config/v850/v850.h (STORE_FLAG_VALUE): Likewise.
* config/xtensa/xtensa.h (STORE_FLAG_VALUE): Likewise.
Co-Authored-By: Zack Weinberg <zack@codesourcery.com>
From-SVN: r67957
Diffstat (limited to 'gcc/config/mcore')
| -rw-r--r-- | gcc/config/mcore/mcore.h | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/gcc/config/mcore/mcore.h b/gcc/config/mcore/mcore.h index 796e9f3..822dfbe 100644 --- a/gcc/config/mcore/mcore.h +++ b/gcc/config/mcore/mcore.h @@ -977,10 +977,6 @@ extern const enum reg_class reg_class_from_letter[]; /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS TARGET_SLOW_BYTES -/* We assume that the store-condition-codes instructions store 0 for false - and some other value for true. This is the value stored for true. */ -#define STORE_FLAG_VALUE 1 - /* Immediate shift counts are truncated by the output routines (or was it the assembler?). Shift counts in a register are truncated by ARM. Note that the native compiler puts too large (> 32) immediate shift counts |