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| author | Richard Henderson <rth@cygnus.com> | 1999-10-14 23:38:02 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 1999-10-14 23:38:02 -0700 |
| commit | 997718c768cbd55f7e2d6a6e8c37ab382dd59c7f (patch) | |
| tree | 6961d842b244b73c4676dcdd51ab81f9796bfce8 /gcc/config/m32r | |
| parent | ffccc6bee2b00018fd09b26a5ce5d0bbc6900e94 (diff) | |
| download | gcc-997718c768cbd55f7e2d6a6e8c37ab382dd59c7f.zip gcc-997718c768cbd55f7e2d6a6e8c37ab382dd59c7f.tar.gz gcc-997718c768cbd55f7e2d6a6e8c37ab382dd59c7f.tar.bz2 | |
1750a.md (movstrqi): Add missing output reload constraint.
* 1750a.md (movstrqi): Add missing output reload constraint.
(call_value): Likewise.
* a29k.md (cpxxx patterns): Add missing match_operator mode.
(jmpfdec): Add missing inout reload constraint.
* elxsi.md (addsi patterns): Add missing output reload constraint.
(move from sp): Use @ alternates.
(call_value): No constraint on output.
* fr30.md (movsi_pop): Add missing output reload constraint.
(movsf_constant_store): Likewise.
(splits): Remove constraints.
(subsi3): Add missing mode.
* i370.md (cmpstrsi+1): Add missing output reload constraint.
(call_value): Likewise.
* i960.md (cmpinc/cmpdec patterns): Add inout reload constraints.
* m32r.h (PREDICATE_CODES): Add seth_add3_operand.
* m32r.md (movsicc_internal): Add output reload constraint.
(movstrsi_internal): Add inout reload constraints.
* m88k.h (reg_names): Don't declare.
(SPECIAL_MODE_PREDICATES): New.
* m88k.md (*): Use register_operand not reg_or_0_operand
on destinations.
* mn10200.h (PREDICATE_CODES): New.
* ns32k.md (ffs pattern): Add output reload constraint.
* pdp11.md (sob pattern): Add inout reload constraint.
* sh.md (splits): Remove constraints.
(indirect_jump_scratch, fpu_switch): Add output reload constraint.
* v850.md (pattern_is_ok_for_epilogue): Likewise.
* vax.md (jgequ pattern): Add inout reload constraint.
From-SVN: r30008
Diffstat (limited to 'gcc/config/m32r')
| -rw-r--r-- | gcc/config/m32r/m32r.h | 3 | ||||
| -rw-r--r-- | gcc/config/m32r/m32r.md | 6 |
2 files changed, 5 insertions, 4 deletions
diff --git a/gcc/config/m32r/m32r.h b/gcc/config/m32r/m32r.h index 4e11838..032e089 100644 --- a/gcc/config/m32r/m32r.h +++ b/gcc/config/m32r/m32r.h @@ -1981,7 +1981,8 @@ enum m32r_function_type { "call_address_operand", { SYMBOL_REF, LABEL_REF, CONST }}, \ { "small_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \ { "m32r_block_immediate_operand",{ CONST_INT }}, \ -{ "large_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, +{ "large_insn_p", { INSN, CALL_INSN, JUMP_INSN }}, \ +{ "seth_add3_operand", { SYMBOL_REF, LABEL_REF, CONST }}, /* Functions declared in m32r.c */ #define XPROTO(ARGS) () diff --git a/gcc/config/m32r/m32r.md b/gcc/config/m32r/m32r.md index bc01b2a..0ad11f0 100644 --- a/gcc/config/m32r/m32r.md +++ b/gcc/config/m32r/m32r.md @@ -1675,7 +1675,7 @@ ;; Generate the conditional instructions based on how the carry flag is examined. (define_insn "*movsicc_internal" - [(set (match_operand:SI 0 "register_operand" "r") + [(set (match_operand:SI 0 "register_operand" "=r") (if_then_else:SI (match_operand 1 "carry_compare_operand" "") (match_operand:SI 2 "conditional_move_operand" "O") (match_operand:SI 3 "conditional_move_operand" "O") @@ -1781,8 +1781,8 @@ ;; Insn generated by block moves (define_insn "movstrsi_internal" - [(set (mem:BLK (match_operand:SI 0 "register_operand" "r")) ;; destination - (mem:BLK (match_operand:SI 1 "register_operand" "r"))) ;; source + [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r")) ;; destination + (mem:BLK (match_operand:SI 1 "register_operand" "+r"))) ;; source (use (match_operand:SI 2 "m32r_block_immediate_operand" "J"));; # bytes to move (set (match_dup 0) (plus:SI (match_dup 0) (minus:SI (match_dup 2) (const_int 4)))) (set (match_dup 1) (plus:SI (match_dup 1) (match_dup 2))) |