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| author | Chen Jiawei <jiawei@iscas.ac.cn> | 2024-03-18 20:54:45 -0600 |
|---|---|---|
| committer | Jeff Law <jlaw@ventanamicro.com> | 2024-03-18 20:56:02 -0600 |
| commit | d91a0cee3611f477730a1fc10beff050dfc800ec (patch) | |
| tree | d6f372e395ae601fd4bac4014bc4a501434107c3 /gcc/config/m32c | |
| parent | c4845edfeaf44756ad9672e8d143f1c8f5c4c0f6 (diff) | |
| download | gcc-d91a0cee3611f477730a1fc10beff050dfc800ec.zip gcc-d91a0cee3611f477730a1fc10beff050dfc800ec.tar.gz gcc-d91a0cee3611f477730a1fc10beff050dfc800ec.tar.bz2 | |
[PATCH] RISC-V: Add XiangShan Nanhu microarchitecture.
This patch add XiangShan Nanhu cpu microarchitecture,
Nanhu is a 6-issue, superscalar, out-of-order processor.
More details see: https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch
gcc/ChangeLog:
* config/riscv/riscv-cores.def (RISCV_TUNE): New def.
(RISCV_CORE): Ditto.
* config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): New
option.
* config/riscv/riscv.cc: New def.
* config/riscv/riscv.md: New include.
* config/riscv/xiangshan.md: New file.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/mcpu-xiangshan-nanhu.c: New test.
Co-Authored by: Lin Jiawei <jiawei.lin@epfl.ch>
Diffstat (limited to 'gcc/config/m32c')
0 files changed, 0 insertions, 0 deletions