addsub.md (addqi3): Disparage a0/a1.

* config/m32c/addsub.md (addqi3): Disparage a0/a1.
(addpsi3): Expand to include memory operands.  Remove
reload-specific splits.
* config/m32c/bitops.md (bset_qi, bset_hi, bclr_qi): New.
(andqi3_16, andhi3_16, iorqi3_16, iorhi3_16): New.
(andqi3_24, andhi3_24, iorqi3_24, iorhi3_24): New.
(andqi3, andhi3, iorqi3, iorhi3): Convert to expanders.
(shift1_qi, shift1_hi, insv): New.
* config/m32c/cond.md (cbranchqi4, cbranchhi4): Remove.
(cbranch<mode>4, stzx_16, stzx_24_<mode>, stzx_reversed,
cmp<mode>, b<code>, s<code>, s<code>_24, movqicc, movhicc,
cond_to_int): New.
* config/m32c/m32c-protos.h: Update as needed.
* config/m32c/m32c.c (m32c_reg_class_from_constraint): Don't
default the Rcr, Rcl, Raw, and Ral constraints.  Add Ra0 and Ra1.
Fail for unrecognized R* constraints.
(m32c_cannot_change_mode_class): Be more picky about pseudos.
(m32c_const_ok_for_constraint_p): Add Imb, Imw, and I00.
(m32c_extra_constraint_p2): Allow (mem (plus (plus fb int) int)).
Add Sp constraint.
(m32c_init_libfuncs): New.
(m32c_legitimate_address_p): Add debug wrapper.
(m32c_rtx_costs): New.
(m32c_address_cost): New.
(conversions): Add 'B' prefix.
(m32c_print_operand): 'h' and 'H' pick lower and upper halves of
operands, or word regnames for QI operands.  'B' prints bit
position.
(m32c_expand_setmemhi): New.
(m32c_expand_movmemhi): New.
(m32c_expand_movstr): New.
(m32c_expand_cmpstr): New.
(m32c_prepare_shift): Shift counts are limited to 16 bits at a time.
(m32c_expand_neg_mulpsi3): Handle non-ints.
(m32c_cmp_flg_0): New.
(m32c_expand_movcc): New.
(m32c_expand_insv): New.
(m32c_scc_pattern): New.
* config/m32c/m32c.h (reg classes): Add AO_REGS and A1_REGS.  Take
a0/a1 out of SIregs.
(STORE_FLAG_VALUE): New.
* config/m32c/m32c.md: Add unspecs for string moves.  Define various mode and
code macros.
(no_insn): New.
* config/m32c/mov.md: Make constraints more liberal.
(zero_extendqihi2): Optimize r0/r1 case.
* config/m32c/muldiv.md (mulpsi3): Check for intvals.
* config/m32c/predicates.md (m32c_any_operand): New.
(m32c_nonimmediate_operand): New.
(m32c_hl_operand): New.
(m32c_r3_operand): New.
(ap_operand): New.
(ma_operand): New.
(memsym_operand): New.
(memimmed_operand): New.
(a_qi_operand): New.
(m32c_eqne_operator): New.
(m32c_1bit8_operand): New.
(m32c_1bit16_operand): New.
(m32c_1mask8_operand): New.
(m32c_1mask16_operand): New.
* config/m32c/blkmov.md: New file.
* config/m32c/t-m32c (MD_FILES): Add blkmov.

From-SVN: r111859

1 files changed, 15 insertions, 41 deletions

diff --git a/gcc/config/m32c/addsub.md b/gcc/config/m32c/addsub.md
index 104709c..6ac31dd 100644
--- a/gcc/config/m32c/addsub.md
+++ b/gcc/config/m32c/addsub.md
@@ -24,22 +24,22 @@
 
 (define_insn "addqi3"
   [(set (match_operand:QI 0 "mra_or_sp_operand"
-		  "=SdRhl,SdRhl,??Rmm,??Rmm, Raa,Raa,SdRhl,??Rmm")
+		  "=SdRhl,SdRhl,??Rmm,??Rmm, *Raa,*Raa,SdRhl,??Rmm")
 	(plus:QI (match_operand:QI 1 "mra_operand"
 		  "%0,0,0,0, 0,0,0,0")
 		 (match_operand:QI 2 "mrai_operand"
-		  "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,Raa,Raa")))]
+		  "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,*Raa,*Raa")))]
   ""
   "add.b\t%2,%0"
   [(set_attr "flags" "oszc")]
   )
 
 (define_insn "addhi3"
-  [(set (match_operand:HI 0 "nonimmediate_operand"
+  [(set (match_operand:HI 0 "m32c_nonimmediate_operand"
 	 	  "=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm, Rhi, Raw, Raw, !Rsp")
-	(plus:HI (match_operand:HI 1 "general_operand"
+	(plus:HI (match_operand:HI 1 "m32c_any_operand"
 		  "%0,0,0,0, 0,0, Raw, Rfb, Rfb, 0")
-		 (match_operand:HI 2 "general_operand"
+		 (match_operand:HI 2 "m32c_any_operand"
 		  "IU2sSdRhi,?Rmm,IU2sSdRhi,?Rmm, IM2,IM2, IS2IU2, I00, IS1, i")))]
   ""
   "@
@@ -57,45 +57,19 @@
   )
 
 (define_insn "addpsi3"
-  [(set (match_operand:PSI 0 "nonimmediate_operand" "=SdRpi,SdRpi,Rsp*Rmm, Rpi,Rpi,Rhi,&Rhi")
-	(plus:PSI (match_operand:PSI 1 "nonimmediate_operand" "0,0,0, Raa,Rad,!Rcl,Rhi")
-		  (match_operand:PSI 2 "general_operand" "iSdRpi,?Rmm,i, i,IS2,i,!Rcl")))]
+  [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=Rpi,Raa,SdRpi,SdRpi,Rsp*Rmm, Rpi,Rpi")
+	(plus:PSI (match_operand:PSI 1 "m32c_nonimmediate_operand" "0,0,0,0,0, Raa,Rad")
+		  (match_operand:PSI 2 "m32c_any_operand" "Is3,IS1,iSdRpi,?Rmm,i, i,IS2")))]
   "TARGET_A24"
   "@
-   add.%&\t%2,%0
-   add.%&\t%2,%0
-   add.%&\t%2,%0
+   add.l:q\t%2,%0
+   addx\t%2,%0
+   add.l\t%2,%0
+   add.l\t%2,%0
+   add.l\t%2,%0
    mova\t%d2[%1],%0
-   mova\t%D2[%1],%0
-   #
-   #"
-  [(set_attr "flags" "oszc,oszc,oszc,*,*,oszc,oszc")]
-  )
-
-; This is needed for reloading large frames.
-(define_split
-  [(set (match_operand:PSI 0 "ra_operand" "")
-	(plus:PSI (match_operand:PSI 1 "cr_operand" "")
-		 (match_operand:PSI 2 "immediate_operand" "")))]
-  ""
-  [(set (match_dup 0) (match_dup 1))
-   (set (match_dup 0)
-	(plus:PSI (match_dup 0)
-		 (match_dup 2)))]
-  ""
-  )
-
-; This is needed for reloading large frames.
-(define_split
-  [(set (match_operand:PSI 0 "ra_operand" "")
-	(plus:PSI (match_operand:PSI 1 "ra_operand" "")
-		 (match_operand:PSI 2 "cr_operand" "")))]
-  ""
-  [(set (match_dup 0) (match_dup 2))
-   (set (match_dup 0)
-	(plus:PSI (match_dup 0)
-		 (match_dup 1)))]
-  ""
+   mova\t%D2[%1],%0"
+  [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,*,*")]
   )
 
 (define_insn "subqi3"