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| author | Chenghui Pan <panchenghui@loongson.cn> | 2023-12-22 16:22:03 +0800 |
|---|---|---|
| committer | Lulu Cheng <chenglulu@loongson.cn> | 2023-12-27 14:54:03 +0800 |
| commit | 183a51935cc9ba1aa0b78f8339edb5f1290320c5 (patch) | |
| tree | c7099eb9189bed1cf42392f3a509038356435a33 /gcc/config/loongarch/loongarch-str.h | |
| parent | 245c9ef2b8574fcaf277416d5986f46c0babbbec (diff) | |
| download | gcc-183a51935cc9ba1aa0b78f8339edb5f1290320c5.zip gcc-183a51935cc9ba1aa0b78f8339edb5f1290320c5.tar.gz gcc-183a51935cc9ba1aa0b78f8339edb5f1290320c5.tar.bz2 | |
LoongArch: Fix insn output of vec_concat templates for LASX.
When investigaing failure of gcc.dg/vect/slp-reduc-sad.c, following
instruction block are being generated by vec_concatv32qi (which is
generated by vec_initv32qiv16qi) at entrance of foo() function:
vldx $vr3,$r5,$r6
vld $vr2,$r5,0
xvpermi.q $xr2,$xr3,0x20
causes the reversion of vec_initv32qiv16qi operation's high and
low 128-bit part.
According to other target's similar impl and LSX impl for following
RTL representation, current definition in lasx.md of "vec_concat<mode>"
are wrong:
(set (op0) (vec_concat (op1) (op2)))
For correct behavior, the last argument of xvpermi.q should be 0x02
instead of 0x20. This patch fixes this issue and cleanup the vec_concat
template impl.
gcc/ChangeLog:
* config/loongarch/lasx.md (vec_concatv4di): Delete.
(vec_concatv8si): Delete.
(vec_concatv16hi): Delete.
(vec_concatv32qi): Delete.
(vec_concatv4df): Delete.
(vec_concatv8sf): Delete.
(vec_concat<mode>): New template with insn output fixed.
Diffstat (limited to 'gcc/config/loongarch/loongarch-str.h')
0 files changed, 0 insertions, 0 deletions