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| author | Steve Ellcey <sje@cup.hp.com> | 2006-02-06 21:27:51 +0000 |
|---|---|---|
| committer | Steve Ellcey <sje@gcc.gnu.org> | 2006-02-06 21:27:51 +0000 |
| commit | 5d48891e67d7c0bbf928c3a96f7730d4fa775884 (patch) | |
| tree | ed43c8424edeff5ed03e218f7b3e72c41eb2aff4 /gcc/config/ia64 | |
| parent | eaa90d25da32a3329c9e434f8117c9122de1fa80 (diff) | |
| download | gcc-5d48891e67d7c0bbf928c3a96f7730d4fa775884.zip gcc-5d48891e67d7c0bbf928c3a96f7730d4fa775884.tar.gz gcc-5d48891e67d7c0bbf928c3a96f7730d4fa775884.tar.bz2 | |
re PR target/25917 (gcc.c-torture/compile/20051228-1.c fails)
PR target/25917
* config/ia64/predicates.md (extr_len_operand): New predicate.
* config/ia64/ia64.md (extv): Tighten constraints.
(extzv): Ditto.
(*tbit_and_2): Ditto.
(*tbit_and_3): Ditto.
(*tbit_or_2): Ditto.
(*tbit_or_3): Ditto.
(*bit_zero): Ditto.
(*bit_one): Ditto.
From-SVN: r110665
Diffstat (limited to 'gcc/config/ia64')
| -rw-r--r-- | gcc/config/ia64/ia64.md | 20 | ||||
| -rw-r--r-- | gcc/config/ia64/predicates.md | 5 |
2 files changed, 15 insertions, 10 deletions
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index afe3e53..da7fe6d 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -1023,8 +1023,8 @@ (define_insn "extv" [(set (match_operand:DI 0 "gr_register_operand" "=r") (sign_extract:DI (match_operand:DI 1 "gr_register_operand" "r") - (match_operand:DI 2 "const_int_operand" "n") - (match_operand:DI 3 "const_int_operand" "n")))] + (match_operand:DI 2 "extr_len_operand" "n") + (match_operand:DI 3 "shift_count_operand" "M")))] "" "extr %0 = %1, %3, %2" [(set_attr "itanium_class" "ishf")]) @@ -1032,8 +1032,8 @@ (define_insn "extzv" [(set (match_operand:DI 0 "gr_register_operand" "=r") (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") - (match_operand:DI 2 "const_int_operand" "n") - (match_operand:DI 3 "const_int_operand" "n")))] + (match_operand:DI 2 "extr_len_operand" "n") + (match_operand:DI 3 "shift_count_operand" "M")))] "" "extr.u %0 = %1, %3, %2" [(set_attr "itanium_class" "ishf")]) @@ -1429,7 +1429,7 @@ (and:BI (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") (const_int 1) - (match_operand:DI 2 "const_int_operand" "n")) + (match_operand:DI 2 "shift_count_operand" "M")) (const_int 0)) (match_operand:BI 3 "register_operand" "0")))] "" @@ -1441,7 +1441,7 @@ (and:BI (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") (const_int 1) - (match_operand:DI 2 "const_int_operand" "n")) + (match_operand:DI 2 "shift_count_operand" "M")) (const_int 0)) (match_operand:BI 3 "register_operand" "0")))] "" @@ -1553,7 +1553,7 @@ (ior:BI (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") (const_int 1) - (match_operand:DI 2 "const_int_operand" "n")) + (match_operand:DI 2 "shift_count_operand" "M")) (const_int 0)) (match_operand:BI 3 "register_operand" "0")))] "" @@ -1565,7 +1565,7 @@ (ior:BI (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") (const_int 1) - (match_operand:DI 2 "const_int_operand" "n")) + (match_operand:DI 2 "shift_count_operand" "M")) (const_int 0)) (match_operand:BI 3 "register_operand" "0")))] "" @@ -5009,7 +5009,7 @@ [(set (match_operand:BI 0 "register_operand" "=c") (eq:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") (const_int 1) - (match_operand:DI 2 "immediate_operand" "n")) + (match_operand:DI 2 "shift_count_operand" "M")) (const_int 0)))] "" "tbit.z %0, %I0 = %1, %2" @@ -5019,7 +5019,7 @@ [(set (match_operand:BI 0 "register_operand" "=c") (ne:BI (zero_extract:DI (match_operand:DI 1 "gr_register_operand" "r") (const_int 1) - (match_operand:DI 2 "immediate_operand" "n")) + (match_operand:DI 2 "shift_count_operand" "M")) (const_int 0)))] "" "tbit.nz %0, %I0 = %1, %2" diff --git a/gcc/config/ia64/predicates.md b/gcc/config/ia64/predicates.md index bdca5fa..ec0f8c3 100644 --- a/gcc/config/ia64/predicates.md +++ b/gcc/config/ia64/predicates.md @@ -486,6 +486,11 @@ (and (match_code "const_int") (match_test "CONST_OK_FOR_M (INTVAL (op))"))) +;; True if OP-1 is a 6 bit immediate operand, used in extr instruction. +(define_predicate "extr_len_operand" + (and (match_code "const_int") + (match_test "CONST_OK_FOR_M (INTVAL (op) - 1)"))) + ;; True if OP is a 5 bit immediate operand. (define_predicate "shift_32bit_count_operand" (and (match_code "const_int") |