diff options
| author | Richard Henderson <rth@redhat.com> | 2010-10-19 10:40:58 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 2010-10-19 10:40:58 -0700 |
| commit | 46935749db5e18fb1d88076b4093099e454a2b3f (patch) | |
| tree | 27c93b1884d048e1981a5a3725fe426e06805f1f /gcc/config/ia64 | |
| parent | 16a1a239c289bb97157a1e1b50ba7b0e3d4a38be (diff) | |
| download | gcc-46935749db5e18fb1d88076b4093099e454a2b3f.zip gcc-46935749db5e18fb1d88076b4093099e454a2b3f.tar.gz gcc-46935749db5e18fb1d88076b4093099e454a2b3f.tar.bz2 | |
Add FMA patterns for ia64.
From-SVN: r165702
Diffstat (limited to 'gcc/config/ia64')
| -rw-r--r-- | gcc/config/ia64/ia64.md | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index db1d2d2..73e57b6 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -2791,6 +2791,36 @@ "TARGET_FUSED_MADD" "fnma.s %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) + +;; Official C99 versions of the fmaf family of operations. +(define_insn "fmasf4" + [(set (match_operand:SF 0 "fr_register_operand" "=f") + (fma:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") + (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") + (match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] + "" + "fma.s %0 = %F1, %F2, %F3" + [(set_attr "itanium_class" "fmac")]) + +(define_insn "*fmssf4" + [(set (match_operand:SF 0 "fr_register_operand" "=f") + (fma:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") + (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") + (neg:SF + (match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))] + "" + "fms.s %0 = %F1, %F2, %F3" + [(set_attr "itanium_class" "fmac")]) + +;; This insn is officially "-(a * b) + c" which is "(-a * b) + c". +(define_insn "*nfmasf4" + [(set (match_operand:SF 0 "fr_register_operand" "=f") + (fma:SF (neg:SF (match_operand:SF 1 "fr_reg_or_fp01_operand" "fG")) + (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG") + (match_operand:SF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] + "" + "fnma.s %0 = %F1, %F2, %F3" + [(set_attr "itanium_class" "fmac")]) ;; :::::::::::::::::::: ;; :: @@ -2977,6 +3007,36 @@ "TARGET_FUSED_MADD" "fnma.s %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) + +;; Official C99 versions of the fma family of operations. +(define_insn "fmadf4" + [(set (match_operand:DF 0 "fr_register_operand" "=f") + (fma:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") + (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") + (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] + "" + "fma.d %0 = %F1, %F2, %F3" + [(set_attr "itanium_class" "fmac")]) + +(define_insn "*fmsdf4" + [(set (match_operand:DF 0 "fr_register_operand" "=f") + (fma:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") + (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") + (neg:DF + (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))] + "" + "fms.d %0 = %F1, %F2, %F3" + [(set_attr "itanium_class" "fmac")]) + +;; See comment for nfmasf4. +(define_insn "*nfmadf4" + [(set (match_operand:DF 0 "fr_register_operand" "=f") + (fma:DF (neg:DF (match_operand:DF 1 "fr_reg_or_fp01_operand" "fG")) + (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG") + (match_operand:DF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] + "" + "fnma.d %0 = %F1, %F2, %F3" + [(set_attr "itanium_class" "fmac")]) ;; :::::::::::::::::::: ;; :: @@ -3234,6 +3294,36 @@ "TARGET_FUSED_MADD" "fnma.d %0 = %F1, %F2, %F3" [(set_attr "itanium_class" "fmac")]) + +;; Official C99 versions of the fmal family of operations. +(define_insn "fmaxf4" + [(set (match_operand:XF 0 "fr_register_operand" "=f") + (fma:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") + (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG") + (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] + "" + "fma %0 = %F1, %F2, %F3" + [(set_attr "itanium_class" "fmac")]) + +(define_insn "*fmsxf4" + [(set (match_operand:XF 0 "fr_register_operand" "=f") + (fma:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") + (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG") + (neg:XF + (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ"))))] + "" + "fms %0 = %F1, %F2, %F3" + [(set_attr "itanium_class" "fmac")]) + +;; See comment for nfmasf4. +(define_insn "*nfmaxf4" + [(set (match_operand:XF 0 "fr_register_operand" "=f") + (fma:XF (neg:XF (match_operand:XF 1 "fr_reg_or_fp01_operand" "fG")) + (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG") + (match_operand:XF 3 "fr_reg_or_signed_fp01_operand" "fZ")))] + "" + "fnma %0 = %F1, %F2, %F3" + [(set_attr "itanium_class" "fmac")]) ;; :::::::::::::::::::: ;; :: |