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| author | Richard Henderson <rth@redhat.com> | 2005-01-27 16:55:07 -0800 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 2005-01-27 16:55:07 -0800 |
| commit | 046625fab2932bdc6827d9abdd895824dfbc80eb (patch) | |
| tree | 3611918a36fd9acca7d65920e977e8e47fd831c5 /gcc/config/ia64/ia64.md | |
| parent | 17a7d6d75a9f752c68a64c1a4f1de8e11b8d3384 (diff) | |
| download | gcc-046625fab2932bdc6827d9abdd895824dfbc80eb.zip gcc-046625fab2932bdc6827d9abdd895824dfbc80eb.tar.gz gcc-046625fab2932bdc6827d9abdd895824dfbc80eb.tar.bz2 | |
builtins.c (expand_builtin_copysign): New.
* builtins.c (expand_builtin_copysign): New.
(expand_builtin): Call it.
* genopinit.c (optabs): Add copysign_optab.
* optabs.c (init_optabs): Initialize it.
(expand_copysign): New.
* optabs.h (OTI_copysign, copysign_optab): New.
(expand_copysign): Declare.
* config/alpha/alpha.md (UNSPEC_COPYSIGN): New.
(copysignsf3, ncopysignsf3, copysigndf3, ncopysigndf3): New.
* config/i386/i386.c (ix86_build_signbit_mask): Split from ...
(ix86_expand_fp_absneg_operator): ... here.
(ix86_split_copysign): New.
* config/i386/i386-protos.h: Update.
* config/i386/i386.md (UNSPEC_COPYSIGN): New.
(copysignsf3, copysigndf3): New.
* config/ia64/ia64.md (UNSPEC_COPYSIGN): New.
(copysignsf3, ncopysignsf3): New.
(copysigndf3, ncopysigndf3): New.
(copysignxf3, ncopysignxf3): New.
* config/ia64/ia64.c (rtx_needs_barrier): Handle UNSPEC_COPYSIGN.
From-SVN: r94357
Diffstat (limited to 'gcc/config/ia64/ia64.md')
| -rw-r--r-- | gcc/config/ia64/ia64.md | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/gcc/config/ia64/ia64.md b/gcc/config/ia64/ia64.md index 90b1cc5..cb5dd10 100644 --- a/gcc/config/ia64/ia64.md +++ b/gcc/config/ia64/ia64.md @@ -78,6 +78,7 @@ (UNSPEC_SETF_EXP 27) (UNSPEC_FR_SQRT_RECIP_APPROX 28) (UNSPEC_SHRP 29) + (UNSPEC_COPYSIGN 30) ]) (define_constants @@ -2586,6 +2587,24 @@ "fnegabs %0 = %1" [(set_attr "itanium_class" "fmisc")]) +(define_insn "copysignsf3" + [(set (match_operand:SF 0 "register_operand" "=f") + (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") + (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] + UNSPEC_COPYSIGN))] + "" + "fmerge.s %0 = %F2, %F1" + [(set_attr "itanium_class" "fmisc")]) + +(define_insn "*ncopysignsf3" + [(set (match_operand:SF 0 "register_operand" "=f") + (neg:SF (unspec:SF [(match_operand:SF 1 "fr_reg_or_fp01_operand" "fG") + (match_operand:SF 2 "fr_reg_or_fp01_operand" "fG")] + UNSPEC_COPYSIGN)))] + "" + "fmerge.ns %0 = %F2, %F1" + [(set_attr "itanium_class" "fmisc")]) + (define_insn "sminsf3" [(set (match_operand:SF 0 "fr_register_operand" "=f") (smin:SF (match_operand:SF 1 "fr_register_operand" "f") @@ -3000,6 +3019,24 @@ "fnegabs %0 = %1" [(set_attr "itanium_class" "fmisc")]) +(define_insn "copysigndf3" + [(set (match_operand:DF 0 "register_operand" "=f") + (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") + (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] + UNSPEC_COPYSIGN))] + "" + "fmerge.s %0 = %F2, %F1" + [(set_attr "itanium_class" "fmisc")]) + +(define_insn "*ncopysigndf3" + [(set (match_operand:DF 0 "register_operand" "=f") + (neg:DF (unspec:DF [(match_operand:DF 1 "fr_reg_or_fp01_operand" "fG") + (match_operand:DF 2 "fr_reg_or_fp01_operand" "fG")] + UNSPEC_COPYSIGN)))] + "" + "fmerge.ns %0 = %F2, %F1" + [(set_attr "itanium_class" "fmisc")]) + (define_insn "smindf3" [(set (match_operand:DF 0 "fr_register_operand" "=f") (smin:DF (match_operand:DF 1 "fr_register_operand" "f") @@ -3556,6 +3593,24 @@ "fnegabs %0 = %F1" [(set_attr "itanium_class" "fmisc")]) +(define_insn "copysignxf3" + [(set (match_operand:XF 0 "register_operand" "=f") + (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") + (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] + UNSPEC_COPYSIGN))] + "" + "fmerge.s %0 = %F2, %F1" + [(set_attr "itanium_class" "fmisc")]) + +(define_insn "*ncopysignxf3" + [(set (match_operand:XF 0 "register_operand" "=f") + (neg:XF (unspec:XF [(match_operand:XF 1 "fr_reg_or_fp01_operand" "fG") + (match_operand:XF 2 "fr_reg_or_fp01_operand" "fG")] + UNSPEC_COPYSIGN)))] + "" + "fmerge.ns %0 = %F2, %F1" + [(set_attr "itanium_class" "fmisc")]) + (define_insn "sminxf3" [(set (match_operand:XF 0 "fr_register_operand" "=f") (smin:XF (match_operand:XF 1 "xfreg_or_fp01_operand" "fG") |