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author | Richard Henderson <rth@redhat.com> | 2002-10-07 01:54:09 -0700 |
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committer | Richard Henderson <rth@gcc.gnu.org> | 2002-10-07 01:54:09 -0700 |
commit | 87cb2a87f80194173484e8ae56b7beb089c19a81 (patch) | |
tree | fd86b0d86f7237fa456967eb08666696c6c1ebab /gcc/config/i960 | |
parent | 5ef38d2ac17d31bec0d881f6a23eb102cccdc213 (diff) | |
download | gcc-87cb2a87f80194173484e8ae56b7beb089c19a81.zip gcc-87cb2a87f80194173484e8ae56b7beb089c19a81.tar.gz gcc-87cb2a87f80194173484e8ae56b7beb089c19a81.tar.bz2 |
i960.md (*): Use TFmode, not XFmode.
* config/i960/i960.md (*): Use TFmode, not XFmode.
* config/i960/i960.c (*): Likewise.
(i960_arg_size_and_align): Remove XFmode alignment hack.
(i960_round_align): Merge code from ROUND_TYPE_ALIGN.
* config/i960/i960.h (LONG_DOUBLE_TYPE_SIZE): Use 128, not 96.
(MAX_LONG_DOUBLE_TYPE_SIZE): Likewise.
(DATA_ALIGNMENT, ROUND_TYPE_SIZE): Remove.
From-SVN: r57889
Diffstat (limited to 'gcc/config/i960')
-rw-r--r-- | gcc/config/i960/i960.c | 32 | ||||
-rw-r--r-- | gcc/config/i960/i960.h | 34 | ||||
-rw-r--r-- | gcc/config/i960/i960.md | 104 |
3 files changed, 75 insertions, 95 deletions
diff --git a/gcc/config/i960/i960.c b/gcc/config/i960/i960.c index 7dbe852..bde6710 100644 --- a/gcc/config/i960/i960.c +++ b/gcc/config/i960/i960.c @@ -152,8 +152,8 @@ i960_initialize () i960_last_maxbitalignment = 8; } - /* Tell the compiler which flavor of XFmode we're using. */ - real_format_for_mode[XFmode - QFmode] = &ieee_extended_intel_96_format; + /* Tell the compiler which flavor of TFmode we're using. */ + real_format_for_mode[TFmode - QFmode] = &ieee_extended_intel_128_format; } /* Return true if OP can be used as the source of an fp move insn. */ @@ -803,13 +803,13 @@ i960_output_ldconst (dst, src) output_asm_insn ("ldconst %1,%0", operands); return ""; } - else if (mode == XFmode) + else if (mode == TFmode) { REAL_VALUE_TYPE d; long value_long[3]; int i; - if (fp_literal_zero (src, XFmode)) + if (fp_literal_zero (src, TFmode)) return "movt 0,%0"; REAL_VALUE_FROM_CONST_DOUBLE (d, src); @@ -2208,7 +2208,7 @@ hard_regno_mode_ok (regno, mode) case DImode: case DFmode: return (regno & 1) == 0; - case TImode: case XFmode: + case TImode: case TFmode: return (regno & 3) == 0; default: @@ -2219,7 +2219,7 @@ hard_regno_mode_ok (regno, mode) { switch (mode) { - case SFmode: case DFmode: case XFmode: + case SFmode: case DFmode: case TFmode: case SCmode: case DCmode: return 1; @@ -2397,14 +2397,7 @@ i960_arg_size_and_align (mode, type, size_out, align_out) size = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; if (type == 0) - { - /* ??? This is a hack to properly correct the alignment of XFmode - values without affecting anything else. */ - if (size == 3) - align = 4; - else - align = size; - } + align = size; else if (TYPE_ALIGN (type) >= BITS_PER_WORD) align = TYPE_ALIGN (type) / BITS_PER_WORD; else @@ -2503,11 +2496,18 @@ i960_object_bytes_bitalign (n) MIN (pragma align, structure size alignment)). */ int -i960_round_align (align, tsize) +i960_round_align (align, type) int align; - tree tsize; + tree type; { int new_align; + tree tsize; + + if (TARGET_OLD_ALIGN || TYPE_PACKED (type)) + return align; + if (TREE_CODE (type) != RECORD_TYPE) + return align; + tsize = TYPE_SIZE (type); if (! tsize || TREE_CODE (tsize) != INTEGER_CST) return align; diff --git a/gcc/config/i960/i960.h b/gcc/config/i960/i960.h index 0c9763f..ee27398 100644 --- a/gcc/config/i960/i960.h +++ b/gcc/config/i960/i960.h @@ -362,17 +362,16 @@ extern int target_flags; /* Width of a word, in units (bytes). */ #define UNITS_PER_WORD 4 -/* Width in bits of a long double. Define to 96, and let - ROUND_TYPE_ALIGN adjust the alignment for speed. */ -#define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 96) -#define MAX_LONG_DOUBLE_TYPE_SIZE 96 +/* Width in bits of a long double. */ +#define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 128) +#define MAX_LONG_DOUBLE_TYPE_SIZE 128 /* Define this to set long double type size to use in libgcc2.c, which can not depend on target_flags. */ #if defined(__LONG_DOUBLE_64__) #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 #else -#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 96 +#define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 #endif /* Allocation boundary (in *bits*) for storing pointers in memory. */ @@ -417,33 +416,14 @@ extern int target_flags; ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \ : (ALIGN)) -/* Make XFmode floating point quantities be 128 bit aligned. */ -#define DATA_ALIGNMENT(TYPE, ALIGN) \ - (TREE_CODE (TYPE) == ARRAY_TYPE \ - && TYPE_MODE (TREE_TYPE (TYPE)) == XFmode \ - && (ALIGN) < 128 ? 128 : (ALIGN)) - /* Macros to determine size of aggregates (structures and unions in C). Normally, these may be defined to simply return the maximum alignment and simple rounded-up size, but on some machines (like the i960), the total size of a structure is based on a non-trivial rounding method. */ -#define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \ - ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \ - ? 128 /* Put 80 bit floating point elements on 128 bit boundaries. */ \ - : ((!TARGET_OLD_ALIGN && !TYPE_PACKED (TYPE) \ - && TREE_CODE (TYPE) == RECORD_TYPE) \ - ? i960_round_align (MAX ((COMPUTED), (SPECIFIED)), TYPE_SIZE (TYPE)) \ - : MAX ((COMPUTED), (SPECIFIED)))) - -#define ROUND_TYPE_SIZE(TYPE, COMPUTED, SPECIFIED) \ - ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \ - ? bitsize_int (128) : round_up (COMPUTED, SPECIFIED)) -#define ROUND_TYPE_SIZE_UNIT(TYPE, COMPUTED, SPECIFIED) \ - ((TREE_CODE (TYPE) == REAL_TYPE && TYPE_MODE (TYPE) == XFmode) \ - ? size_int (16) : round_up (COMPUTED, SPECIFIED)) - +#define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \ + i960_round_align (MAX ((COMPUTED), (SPECIFIED)), TYPE) /* Standard register usage. */ @@ -526,7 +506,7 @@ extern int target_flags; /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On 80960, the cpu registers can hold any mode but the float registers - can only hold SFmode, DFmode, or XFmode. */ + can only hold SFmode, DFmode, or TFmode. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok ((REGNO), (MODE)) /* Value is 1 if it is a good idea to tie two pseudo registers diff --git a/gcc/config/i960/i960.md b/gcc/config/i960/i960.md index c5b32da..af0193f 100644 --- a/gcc/config/i960/i960.md +++ b/gcc/config/i960/i960.md @@ -2061,10 +2061,10 @@ ;; Tetra (16 byte) float support. -(define_expand "cmpxf" +(define_expand "cmptf" [(set (reg:CC 36) - (compare:CC (match_operand:XF 0 "register_operand" "") - (match_operand:XF 1 "nonmemory_operand" "")))] + (compare:CC (match_operand:TF 0 "register_operand" "") + (match_operand:TF 1 "nonmemory_operand" "")))] "TARGET_NUMERICS" " { @@ -2075,27 +2075,27 @@ (define_insn "" [(set (reg:CC 36) - (compare:CC (match_operand:XF 0 "register_operand" "f") - (match_operand:XF 1 "nonmemory_operand" "fGH")))] + (compare:CC (match_operand:TF 0 "register_operand" "f") + (match_operand:TF 1 "nonmemory_operand" "fGH")))] "TARGET_NUMERICS" "cmpr %0,%1" [(set_attr "type" "fpcc")]) -(define_expand "movxf" - [(set (match_operand:XF 0 "general_operand" "") - (match_operand:XF 1 "fpmove_src_operand" ""))] +(define_expand "movtf" + [(set (match_operand:TF 0 "general_operand" "") + (match_operand:TF 1 "fpmove_src_operand" ""))] "" " { - if (emit_move_sequence (operands, XFmode)) + if (emit_move_sequence (operands, TFmode)) DONE; }") (define_insn "" - [(set (match_operand:XF 0 "general_operand" "=r,f,d,d,m") - (match_operand:XF 1 "fpmove_src_operand" "r,GH,F,m,d"))] - "register_operand (operands[0], XFmode) - || register_operand (operands[1], XFmode)" + [(set (match_operand:TF 0 "general_operand" "=r,f,d,d,m") + (match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,d"))] + "register_operand (operands[0], TFmode) + || register_operand (operands[1], TFmode)" "* { switch (which_alternative) @@ -2119,9 +2119,9 @@ }" [(set_attr "type" "move,move,load,fpload,fpstore")]) -(define_insn "extendsfxf2" - [(set (match_operand:XF 0 "register_operand" "=f,d") - (float_extend:XF +(define_insn "extendsftf2" + [(set (match_operand:TF 0 "register_operand" "=f,d") + (float_extend:TF (match_operand:SF 1 "register_operand" "d,f")))] "TARGET_NUMERICS" "@ @@ -2129,9 +2129,9 @@ movre %1,%0" [(set_attr "type" "fpmove")]) -(define_insn "extenddfxf2" - [(set (match_operand:XF 0 "register_operand" "=f,d") - (float_extend:XF +(define_insn "extenddftf2" + [(set (match_operand:TF 0 "register_operand" "=f,d") + (float_extend:TF (match_operand:DF 1 "register_operand" "d,f")))] "TARGET_NUMERICS" "@ @@ -2139,85 +2139,85 @@ movre %1,%0" [(set_attr "type" "fpmove")]) -(define_insn "truncxfdf2" +(define_insn "trunctfdf2" [(set (match_operand:DF 0 "register_operand" "=d") (float_truncate:DF - (match_operand:XF 1 "register_operand" "f")))] + (match_operand:TF 1 "register_operand" "f")))] "TARGET_NUMERICS" "movrl %1,%0" [(set_attr "type" "fpmove")]) -(define_insn "truncxfsf2" +(define_insn "trunctfsf2" [(set (match_operand:SF 0 "register_operand" "=d") (float_truncate:SF - (match_operand:XF 1 "register_operand" "f")))] + (match_operand:TF 1 "register_operand" "f")))] "TARGET_NUMERICS" "movr %1,%0" [(set_attr "type" "fpmove")]) -(define_insn "floatsixf2" - [(set (match_operand:XF 0 "register_operand" "=f") - (float:XF (match_operand:SI 1 "register_operand" "d")))] +(define_insn "floatsitf2" + [(set (match_operand:TF 0 "register_operand" "=f") + (float:TF (match_operand:SI 1 "register_operand" "d")))] "TARGET_NUMERICS" "cvtir %1,%0" [(set_attr "type" "fpcvt")]) -(define_insn "fix_truncxfsi2" +(define_insn "fix_trunctfsi2" [(set (match_operand:SI 0 "register_operand" "=d") - (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))] + (fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))] "TARGET_NUMERICS" "cvtzri %1,%0" [(set_attr "type" "fpcvt")]) -(define_insn "fixuns_truncxfsi2" +(define_insn "fixuns_trunctfsi2" [(set (match_operand:SI 0 "register_operand" "=d") - (unsigned_fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))] + (unsigned_fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))] "TARGET_NUMERICS" "cvtzri %1,%0" [(set_attr "type" "fpcvt")]) -(define_insn "addxf3" - [(set (match_operand:XF 0 "register_operand" "=f") - (plus:XF (match_operand:XF 1 "nonmemory_operand" "%fGH") - (match_operand:XF 2 "nonmemory_operand" "fGH")))] +(define_insn "addtf3" + [(set (match_operand:TF 0 "register_operand" "=f") + (plus:TF (match_operand:TF 1 "nonmemory_operand" "%fGH") + (match_operand:TF 2 "nonmemory_operand" "fGH")))] "TARGET_NUMERICS" "addr %1,%2,%0" [(set_attr "type" "fpadd")]) -(define_insn "subxf3" - [(set (match_operand:XF 0 "register_operand" "=f") - (minus:XF (match_operand:XF 1 "nonmemory_operand" "fGH") - (match_operand:XF 2 "nonmemory_operand" "fGH")))] +(define_insn "subtf3" + [(set (match_operand:TF 0 "register_operand" "=f") + (minus:TF (match_operand:TF 1 "nonmemory_operand" "fGH") + (match_operand:TF 2 "nonmemory_operand" "fGH")))] "TARGET_NUMERICS" "subr %2,%1,%0" [(set_attr "type" "fpadd")]) -(define_insn "mulxf3" - [(set (match_operand:XF 0 "register_operand" "=f") - (mult:XF (match_operand:XF 1 "nonmemory_operand" "%fGH") - (match_operand:XF 2 "nonmemory_operand" "fGH")))] +(define_insn "multf3" + [(set (match_operand:TF 0 "register_operand" "=f") + (mult:TF (match_operand:TF 1 "nonmemory_operand" "%fGH") + (match_operand:TF 2 "nonmemory_operand" "fGH")))] "TARGET_NUMERICS" "mulr %1,%2,%0" [(set_attr "type" "fpmul")]) -(define_insn "divxf3" - [(set (match_operand:XF 0 "register_operand" "=f") - (div:XF (match_operand:XF 1 "nonmemory_operand" "fGH") - (match_operand:XF 2 "nonmemory_operand" "fGH")))] +(define_insn "divtf3" + [(set (match_operand:TF 0 "register_operand" "=f") + (div:TF (match_operand:TF 1 "nonmemory_operand" "fGH") + (match_operand:TF 2 "nonmemory_operand" "fGH")))] "TARGET_NUMERICS" "divr %2,%1,%0" [(set_attr "type" "fpdiv")]) -(define_insn "negxf2" - [(set (match_operand:XF 0 "register_operand" "=f") - (neg:XF (match_operand:XF 1 "register_operand" "f")))] +(define_insn "negtf2" + [(set (match_operand:TF 0 "register_operand" "=f") + (neg:TF (match_operand:TF 1 "register_operand" "f")))] "TARGET_NUMERICS" "subr %1,0f0.0,%0" [(set_attr "type" "fpadd")]) -(define_insn "absxf2" - [(set (match_operand:XF 0 "register_operand" "=f") - (abs:XF (match_operand:XF 1 "register_operand" "f")))] +(define_insn "abstf2" + [(set (match_operand:TF 0 "register_operand" "=f") + (abs:TF (match_operand:TF 1 "register_operand" "f")))] "(TARGET_NUMERICS)" "cpysre %1,0f0.0,%0" [(set_attr "type" "fpmove")]) |