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| author | H.J. Lu <hongjiu.lu@intel.com> | 2018-10-20 20:41:10 +0000 |
|---|---|---|
| committer | H.J. Lu <hjl@gcc.gnu.org> | 2018-10-20 13:41:10 -0700 |
| commit | fda5d5e6e040d23e7e751a491097090b8f5ff58a (patch) | |
| tree | f21739a7d53f96d5b4ff0024e083bdc602a49375 /gcc/config/i386 | |
| parent | f65c0c735ee8abb8669193571a491fb407bac11d (diff) | |
| download | gcc-fda5d5e6e040d23e7e751a491097090b8f5ff58a.zip gcc-fda5d5e6e040d23e7e751a491097090b8f5ff58a.tar.gz gcc-fda5d5e6e040d23e7e751a491097090b8f5ff58a.tar.bz2 | |
i386: Enable AVX512 memory broadcast for FP div
Many AVX512 vector operations can broadcast from a scalar memory source.
This patch enables memory broadcast for FP div operations.
gcc/
PR target/72782
* config/i386/sse.md (*<avx512>_div<mode>3<mask_name>_bcst): New.
gcc/testsuite/
PR target/72782
* gcc.target/i386/avx512f-div-df-zmm-1.c: New test.
* gcc.target/i386/avx512f-div-sf-zmm-1.c: Likewise.
* gcc.target/i386/avx512f-div-sf-zmm-2.c: Likewise.
* gcc.target/i386/avx512f-div-sf-zmm-3.c: Likewise.
* gcc.target/i386/avx512f-div-sf-zmm-4.c: Likewise.
* gcc.target/i386/avx512f-div-sf-zmm-5.c: Likewise.
* gcc.target/i386/avx512vl-div-sf-xmm-1.c: Likewise.
* gcc.target/i386/avx512vl-div-sf-ymm-1.c: Likewise.
From-SVN: r265345
Diffstat (limited to 'gcc/config/i386')
| -rw-r--r-- | gcc/config/i386/sse.md | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 411c78a..1b41aa5 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1812,6 +1812,18 @@ (set_attr "prefix" "<mask_prefix3>") (set_attr "mode" "<MODE>")]) +(define_insn "*<avx512>_div<mode>3<mask_name>_bcst" + [(set (match_operand:VF_AVX512 0 "register_operand" "=v") + (div:VF_AVX512 + (match_operand:VF_AVX512 1 "register_operand" "v") + (vec_duplicate:VF_AVX512 + (match_operand:<ssescalarmode> 2 "memory_operand" "m"))))] + "TARGET_AVX512F && <mask_mode512bit_condition>" + "vdiv<ssemodesuffix>\t{%2<avx512bcst>, %1, %0<mask_operand3>|%0<mask_operand3>, %1, %2<<avx512bcst>>}" + [(set_attr "prefix" "evex") + (set_attr "type" "ssediv") + (set_attr "mode" "<MODE>")]) + (define_insn "<sse>_rcp<mode>2" [(set (match_operand:VF1_128_256 0 "register_operand" "=x") (unspec:VF1_128_256 |