re PR inline-asm/39590 (inline asm %z on amd64 says "ll" instead of "q")

	PR target/39590
	* configure.ac (HAVE_AS_IX86_FILDQ): On x86 targets check whether
	the configured assembler supports fildq and fistpq mnemonics.
	(HAVE_AS_IX86_FILDS): Rename from HAVE_GAS_FILDS_FISTS.
	* configure: Regenerated.
	* config.in: Ditto.

	* config/i386/i386.c (print_operand): Handle 'Z'.
	['z']: Remove handling of special fild/fist suffixes.
	(output_fix_trunc): Use '%Z' to output suffix of fist{,p,tp} insn.
	* config/i386/i386.md (*floathi<mode>2_i387): Use '%Z' to output
	suffix of fild insn.
	(*floatsi<mode>2_vector_mixed): Ditto.
	(*float<SSEMODEI24:mode><MODEF:mode>2_mixed_interunit): Ditto.
	(*float<SSEMODEI24:mode><MODEF:mode>2_mixed_nointerunit): Ditto.
	(*float<SSEMODEI24:mode><X87MODEF:mode>2_i387_with_temp): Ditto.
	(*float<SSEMODEI24:mode><X87MODEF:mode>2_i387): Ditto.
	* config/i386/gas.h (GAS_MNEMONICS): Remove.

From-SVN: r146761

3 files changed, 84 insertions, 61 deletions

diff --git a/gcc/config/i386/gas.h b/gcc/config/i386/gas.h
index f3d43b3..c4dafc6 100644
--- a/gcc/config/i386/gas.h
+++ b/gcc/config/i386/gas.h
@@ -117,9 +117,6 @@ along with GCC; see the file COPYING3.  If not see
 #undef SHIFT_DOUBLE_OMITS_COUNT
 #define SHIFT_DOUBLE_OMITS_COUNT 0
 
-/* Print opcodes the way that GAS expects them.  */
-#define GAS_MNEMONICS 1
-
 /* The comment-starter string as GAS expects it. */
 #undef ASM_COMMENT_START
 #define ASM_COMMENT_START "#"
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index ab851dc..65ee05c 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -10848,6 +10848,7 @@ get_some_local_dynamic_name (void)
         otherwise nothing
    R -- print the prefix for register names.
    z -- print the opcode suffix for the size of the current operand.
+   Z -- likewise, with special suffixes for fild/fist instructions.
    * -- print a star (in certain assembler syntax)
    A -- print an absolute memory reference.
    w -- print the operand as if it's a "word" (HImode) even if it isn't.
@@ -10946,6 +10947,37 @@ print_operand (FILE *file, rtx x, int code)
 	    putc ('t', file);
 	  return;
 
+	case 'Z':
+	  gcc_assert (MEM_P (x));
+
+	  /* fild/fist don't get size suffixes if using Intel opcodes.  */
+	  if (ASSEMBLER_DIALECT == ASM_INTEL)
+	    return;
+
+	  switch (GET_MODE_SIZE (GET_MODE (x)))
+	    {
+	    case 2:
+#ifdef HAVE_AS_IX86_FILDS
+	      putc ('s', file);
+#endif
+	      return;
+
+	    case 4:
+	      putc ('l', file);
+	      return;
+
+	    case 8:
+#ifdef HAVE_AS_IX86_FILDQ
+	      putc ('q', file);
+#else
+	      fputs ("ll", file);
+#endif
+	      return;
+
+	    default:
+	      gcc_unreachable ();
+	    }
+	    
 	case 'z':
 	  /* 387 opcodes don't get size suffixes if the operands are
 	     registers.  */
@@ -10964,51 +10996,28 @@ print_operand (FILE *file, rtx x, int code)
 	      return;
 
 	    case 2:
-	      if (MEM_P (x))
-		{
-#ifdef HAVE_GAS_FILDS_FISTS
-		  putc ('s', file);
-#endif
-		  return;
-		}
-	      else
-		putc ('w', file);
+	      putc ('w', file);
 	      return;
 
 	    case 4:
-	      if (GET_MODE (x) == SFmode)
-		{
-		  putc ('s', file);
-		  return;
-		}
-	      else
+	      if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
 		putc ('l', file);
-	      return;
-
-	    case 12:
-	    case 16:
-	      putc ('t', file);
+	      else
+		putc ('s', file);
 	      return;
 
 	    case 8:
 	      if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT)
-		{
-		  if (MEM_P (x))
-		    {
-#ifdef GAS_MNEMONICS
-		      putc ('q', file);
-#else
-		      putc ('l', file);
-		      putc ('l', file);
-#endif
-		    }
-		  else
-		    putc ('q', file);
-		}
+		putc ('q', file);
 	      else
 	        putc ('l', file);
 	      return;
 
+	    case 12:
+	    case 16:
+	      putc ('t', file);
+	      return;
+
 	    default:
 	      gcc_unreachable ();
 	    }
@@ -12089,15 +12098,15 @@ output_fix_trunc (rtx insn, rtx *operands, int fisttp)
   gcc_assert (GET_MODE (operands[1]) != TFmode);
 
   if (fisttp)
-      output_asm_insn ("fisttp%z0\t%0", operands);
+      output_asm_insn ("fisttp%Z0\t%0", operands);
   else
     {
       if (round_mode != I387_CW_ANY)
 	output_asm_insn ("fldcw\t%3", operands);
       if (stack_top_dies || dimode_p)
-	output_asm_insn ("fistp%z0\t%0", operands);
+	output_asm_insn ("fistp%Z0\t%0", operands);
       else
-	output_asm_insn ("fist%z0\t%0", operands);
+	output_asm_insn ("fist%Z0\t%0", operands);
       if (round_mode != I387_CW_ANY)
 	output_asm_insn ("fldcw\t%2", operands);
     }
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 777a72c..d315580 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -27,22 +27,39 @@
 ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
 ;;
 ;; The special asm out single letter directives following a '%' are:
-;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of
-;;     operands[1].
-;; 'L' Print the opcode suffix for a 32-bit integer opcode.
-;; 'W' Print the opcode suffix for a 16-bit integer opcode.
-;; 'B' Print the opcode suffix for an 8-bit integer opcode.
-;; 'Q' Print the opcode suffix for a 64-bit float opcode.
-;; 'S' Print the opcode suffix for a 32-bit float opcode.
-;; 'T' Print the opcode suffix for an 80-bit extended real XFmode float opcode.
-;; 'J' Print the appropriate jump operand.
-;;
-;; 'b' Print the QImode name of the register for the indicated operand.
-;;     %b0 would print %al if operands[0] is reg 0.
-;; 'w' Likewise, print the HImode name of the register.
-;; 'k' Likewise, print the SImode name of the register.
-;; 'h' Print the QImode name for a "high" register, either ah, bh, ch or dh.
-;; 'y' Print "st(0)" instead of "st" as a register.
+;; L,W,B,Q,S,T -- print the opcode suffix for specified size of operand.
+;; C -- print opcode suffix for set/cmov insn.
+;; c -- like C, but print reversed condition
+;; E,e -- likewise, but for compare-and-branch fused insn.
+;; F,f -- likewise, but for floating-point.
+;; O -- if HAVE_AS_IX86_CMOV_SUN_SYNTAX, expand to "w.", "l." or "q.",
+;;      otherwise nothing
+;; R -- print the prefix for register names.
+;; z -- print the opcode suffix for the size of the current operand.
+;; Z -- likewise, with special suffixes for fild/fist instructions.
+;; * -- print a star (in certain assembler syntax)
+;; A -- print an absolute memory reference.
+;; w -- print the operand as if it's a "word" (HImode) even if it isn't.
+;; s -- print a shift double count, followed by the assemblers argument
+;;	delimiter.
+;; b -- print the QImode name of the register for the indicated operand.
+;;	%b0 would print %al if operands[0] is reg 0.
+;; w --  likewise, print the HImode name of the register.
+;; k --  likewise, print the SImode name of the register.
+;; q --  likewise, print the DImode name of the register.
+;; x --  likewise, print the V4SFmode name of the register.
+;; t --  likewise, print the V8SFmode name of the register.
+;; h -- print the QImode name for a "high" register, either ah, bh, ch or dh.
+;; y -- print "st(0)" instead of "st" as a register.
+;; d -- print duplicated register operand for AVX instruction.
+;; D -- print condition for SSE cmp instruction.
+;; P -- if PIC, print an @PLT suffix.
+;; X -- don't print any sort of PIC '@' suffix for a symbol.
+;; & -- print some in-use local-dynamic symbol name.
+;; H -- print a memory address offset by 8; used for sse high-parts
+;; Y -- print condition for SSE5 com* instruction.
+;; + -- print a branch hint as 'cs' or 'ds' prefix
+;; ; -- print a semicolon (after prefixes due to bug in older gas).
 
 ;; UNSPEC usage:
 
@@ -5124,7 +5141,7 @@
   "TARGET_80387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
        || TARGET_MIX_SSE_I387)"
-  "fild%z1\t%1"
+  "fild%Z1\t%1"
   [(set_attr "type" "fmov")
    (set_attr "mode" "<MODE>")
    (set_attr "fp_int_src" "true")])
@@ -5234,7 +5251,7 @@
   "TARGET_SSE2 && TARGET_MIX_SSE_I387
    && TARGET_USE_VECTOR_CONVERTS && optimize_function_for_speed_p (cfun)"
   "@
-   fild%z1\t%1
+   fild%Z1\t%1
    #"
   [(set_attr "type" "fmov,sseicvt")
    (set_attr "mode" "<MODE>,<ssevecmode>")
@@ -5295,7 +5312,7 @@
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
    && (TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
   "@
-   fild%z1\t%1
+   fild%Z1\t%1
    %vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}
    %vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
   [(set_attr "type" "fmov,sseicvt,sseicvt")
@@ -5314,7 +5331,7 @@
    && SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_MIX_SSE_I387
    && !(TARGET_INTER_UNIT_CONVERSIONS || optimize_function_for_size_p (cfun))"
   "@
-   fild%z1\t%1
+   fild%Z1\t%1
    %vcvtsi2s<MODEF:ssemodefsuffix><SSEMODEI24:rex64suffix>\t{%1, %d0|%d0, %1}"
   [(set_attr "type" "fmov,sseicvt")
    (set_attr "prefix" "orig,maybe_vex")
@@ -5564,7 +5581,7 @@
   "TARGET_80387
    && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)"
   "@
-   fild%z1\t%1
+   fild%Z1\t%1
    #"
   [(set_attr "type" "fmov,multi")
    (set_attr "mode" "<X87MODEF:MODE>")
@@ -5577,7 +5594,7 @@
 	  (match_operand:SSEMODEI24 1 "memory_operand" "m")))]
   "TARGET_80387
    && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)"
-  "fild%z1\t%1"
+  "fild%Z1\t%1"
   [(set_attr "type" "fmov")
    (set_attr "mode" "<X87MODEF:MODE>")
    (set_attr "fp_int_src" "true")])