ix86: Don't use the 'm' constraint for x86_64_general_operand

The 'm' constraint is defined with define_memory_constraint which allows
LRA to convert the operand to the form '(mem (reg X))', where X is a
base register.  To prevent LRA from generating '(mem (reg X))' from a
register:

1. Add a 'BM' constraint which is similar to the 'm' constraint, but
is defined with define_constraint.
2. Add a 'm' mode attribute which is mapped to the 'm' constraint for
general_operand and the 'BM' constraint for x86_64_general_operand.
3. Replace the 'm' constraint on <general_operand> with the '<m>'
constraint.
4. Replace the 'm' constraint on x86_64_general_operand with the 'BM'
constraint.

gcc/

	PR target/103762
	* config/i386/constraints.md (BM): New constraint.
	* config/i386/i386.md (m): New mode attribute.
	Replace the 'm' constraint on <general_operand> with the '<m>'
	constraint.
	Replace the 'm' constraint on x86_64_general_operand with the
	'BM' constraint.

gcc/testsuite/

	* gcc.target/i386/pr103762-1a.c: New test.
	* gcc.target/i386/pr103762-1b.c: Likewise.
	* gcc.target/i386/pr103762-1c.c: Likewise.

2 files changed, 45 insertions, 32 deletions

diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
index 6b291a0..ded2e19 100644
--- a/gcc/config/i386/constraints.md
+++ b/gcc/config/i386/constraints.md
@@ -168,6 +168,7 @@
 ;;  z  Constant call address operand.
 ;;  C  Integer SSE constant with all bits set operand.
 ;;  F  Floating-point SSE constant with all bits set operand.
+;;  M  x86-64 memory operand.
 
 (define_constraint "Bf"
   "@internal Flags register operand."
@@ -232,6 +233,15 @@
   (and (match_test "TARGET_SSE")
        (match_operand 0 "float_vector_all_ones_operand")))
 
+;; NB: Similar to 'm', but don't use define_memory_constraint on x86-64
+;; to prevent LRA from converting the operand to the form '(mem (reg X))'
+;; where X is a base register.
+(define_constraint "BM"
+  "@internal x86-64 memory operand."
+  (and (match_code "mem")
+       (match_test "memory_address_addr_space_p (GET_MODE (op), XEXP (op, 0),
+						 MEM_ADDR_SPACE (op))")))
+
 ;; Integer constant constraints.
 (define_constraint "Wb"
   "Integer constant in the range 0 @dots{} 7, for 8-bit shifts."
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index eea5d5d..e670e7d 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -1148,6 +1148,9 @@
 ;; General operand constraint for word modes.
 (define_mode_attr g [(QI "qmn") (HI "rmn") (SI "rme") (DI "rme")])
 
+;; Memory operand constraint for word modes.
+(define_mode_attr m [(QI "m") (HI "m") (SI "BM") (DI "BM")])
+
 ;; Immediate operand constraint for double integer modes.
 (define_mode_attr di [(SI "nF") (DI "Wd")])
 
@@ -1390,7 +1393,7 @@
 (define_insn "*cmp<mode>_1"
   [(set (reg FLAGS_REG)
 	(compare (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
-		 (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m")))]
+		 (match_operand:SWI 1 "<general_operand>" "<r><i>,<r><m>")))]
   "ix86_match_ccmode (insn, CCmode)"
   "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
   [(set_attr "type" "icmp")
@@ -1400,7 +1403,7 @@
   [(set (reg FLAGS_REG)
 	(compare
 	  (minus:SWI (match_operand:SWI 0 "nonimmediate_operand" "<r>m,<r>")
-		     (match_operand:SWI 1 "<general_operand>" "<r><i>,<r>m"))
+		     (match_operand:SWI 1 "<general_operand>" "<r><i>,<r><m>"))
 	  (const_int 0)))]
   "ix86_match_ccmode (insn, CCGOCmode)"
   "cmp{<imodesuffix>}\t{%1, %0|%0, %1}"
@@ -5684,7 +5687,7 @@
   [(set (match_operand:SWI48 0 "nonimmediate_operand" "=rm,r,r,r")
 	(plus:SWI48
 	  (match_operand:SWI48 1 "nonimmediate_operand" "%0,0,r,r")
-	  (match_operand:SWI48 2 "x86_64_general_operand" "re,m,0,le")))
+	  (match_operand:SWI48 2 "x86_64_general_operand" "re,BM,0,le")))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
 {
@@ -5740,7 +5743,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r,r,r")
 	(zero_extend:DI
 	  (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r,r")
-		   (match_operand:SI 2 "x86_64_general_operand" "rme,0,le"))))
+		   (match_operand:SI 2 "x86_64_general_operand" "rBMe,0,le"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
 {
@@ -5998,7 +6001,7 @@
 	(compare
 	  (plus:SWI
 	    (match_operand:SWI 1 "nonimmediate_operand" "%0,0,<r>")
-	    (match_operand:SWI 2 "<general_operand>" "<r><i>,m,0"))
+	    (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>,0"))
 	  (const_int 0)))
    (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>,<r>")
 	(plus:SWI (match_dup 1) (match_dup 2)))]
@@ -6043,7 +6046,7 @@
   [(set (reg FLAGS_REG)
 	(compare
 	  (plus:SI (match_operand:SI 1 "nonimmediate_operand" "%0,r")
-		   (match_operand:SI 2 "x86_64_general_operand" "rme,0"))
+		   (match_operand:SI 2 "x86_64_general_operand" "rBMe,0"))
 	  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r,r")
 	(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
@@ -6128,7 +6131,7 @@
 (define_insn "*addsi_3_zext"
   [(set (reg FLAGS_REG)
 	(compare
-	  (neg:SI (match_operand:SI 2 "x86_64_general_operand" "rme,0"))
+	  (neg:SI (match_operand:SI 2 "x86_64_general_operand" "rBMe,0"))
 	  (match_operand:SI 1 "nonimmediate_operand" "%0,r")))
    (set (match_operand:DI 0 "register_operand" "=r,r")
 	(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
@@ -6832,7 +6835,7 @@
   [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
 	(minus:SWI
 	  (match_operand:SWI 1 "nonimmediate_operand" "0,0")
-	  (match_operand:SWI 2 "<general_operand>" "<r><i>,m")))
+	  (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>")))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
   "sub{<imodesuffix>}\t{%2, %0|%0, %2}"
@@ -6843,7 +6846,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI
 	  (minus:SI (match_operand:SI 1 "register_operand" "0")
-		    (match_operand:SI 2 "x86_64_general_operand" "rme"))))
+		    (match_operand:SI 2 "x86_64_general_operand" "rBMe"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
   "sub{l}\t{%2, %k0|%k0, %2}"
@@ -6875,7 +6878,7 @@
 	(compare
 	  (minus:SWI
 	    (match_operand:SWI 1 "nonimmediate_operand" "0,0")
-	    (match_operand:SWI 2 "<general_operand>" "<r><i>,m"))
+	    (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>"))
 	  (const_int 0)))
    (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
 	(minus:SWI (match_dup 1) (match_dup 2)))]
@@ -6889,7 +6892,7 @@
   [(set (reg FLAGS_REG)
 	(compare
 	  (minus:SI (match_operand:SI 1 "register_operand" "0")
-		    (match_operand:SI 2 "x86_64_general_operand" "rme"))
+		    (match_operand:SI 2 "x86_64_general_operand" "rBMe"))
 	  (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI
@@ -7142,7 +7145,7 @@
 (define_insn "*sub<mode>_3"
   [(set (reg FLAGS_REG)
 	(compare (match_operand:SWI 1 "nonimmediate_operand" "0,0")
-		 (match_operand:SWI 2 "<general_operand>" "<r><i>,m")))
+		 (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>")))
    (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
 	(minus:SWI (match_dup 1) (match_dup 2)))]
   "ix86_match_ccmode (insn, CCmode)
@@ -7218,7 +7221,7 @@
 (define_insn "*subsi_3_zext"
   [(set (reg FLAGS_REG)
 	(compare (match_operand:SI 1 "register_operand" "0")
-		 (match_operand:SI 2 "x86_64_general_operand" "rme")))
+		 (match_operand:SI 2 "x86_64_general_operand" "rBMe")))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI
 	  (minus:SI (match_dup 1)
@@ -7238,7 +7241,7 @@
 	    (match_operator:SWI 4 "ix86_carry_flag_operator"
 	     [(match_operand 3 "flags_reg_operand") (const_int 0)])
 	    (match_operand:SWI 1 "nonimmediate_operand" "%0,0"))
-	  (match_operand:SWI 2 "<general_operand>" "<r><i>,m")))
+	  (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>")))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (PLUS, <MODE>mode, operands)"
   "adc{<imodesuffix>}\t{%2, %0|%0, %2}"
@@ -7282,7 +7285,7 @@
 	    (plus:SI (match_operator:SI 3 "ix86_carry_flag_operator"
 		      [(reg FLAGS_REG) (const_int 0)])
 		     (match_operand:SI 1 "register_operand" "%0"))
-	    (match_operand:SI 2 "x86_64_general_operand" "rme"))))
+	    (match_operand:SI 2 "x86_64_general_operand" "rBMe"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (PLUS, SImode, operands)"
   "adc{l}\t{%2, %k0|%k0, %2}"
@@ -7408,7 +7411,7 @@
 	    (match_operand:SWI 1 "nonimmediate_operand" "0,0")
 	    (match_operator:SWI 4 "ix86_carry_flag_operator"
 	     [(match_operand 3 "flags_reg_operand") (const_int 0)]))
-	  (match_operand:SWI 2 "<general_operand>" "<r><i>,m")))
+	  (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>")))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (MINUS, <MODE>mode, operands)"
   "sbb{<imodesuffix>}\t{%2, %0|%0, %2}"
@@ -7453,7 +7456,7 @@
 	      (match_operand:SI 1 "register_operand" "0")
 	      (match_operator:SI 3 "ix86_carry_flag_operator"
 	       [(reg FLAGS_REG) (const_int 0)]))
-	    (match_operand:SI 2 "x86_64_general_operand" "rme"))))
+	    (match_operand:SI 2 "x86_64_general_operand" "rBMe"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (MINUS, SImode, operands)"
   "sbb{l}\t{%2, %k0|%k0, %2}"
@@ -7529,7 +7532,7 @@
 (define_insn "@sub<mode>3_carry_ccgz"
   [(set (reg:CCGZ FLAGS_REG)
 	(unspec:CCGZ [(match_operand:DWIH 1 "register_operand" "0")
-		      (match_operand:DWIH 2 "x86_64_general_operand" "rme")
+		      (match_operand:DWIH 2 "x86_64_general_operand" "rBMe")
 		      (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))]
 		     UNSPEC_SBB))
    (clobber (match_scratch:DWIH 0 "=r"))]
@@ -7616,7 +7619,7 @@
 	(compare:CCC
 	    (plus:SWI
 		(match_operand:SWI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:SWI 2 "<general_operand>" "<r><i>,m"))
+		(match_operand:SWI 2 "<general_operand>" "<r><i>,<m>"))
 	    (match_dup 1)))
    (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
 	(plus:SWI (match_dup 1) (match_dup 2)))]
@@ -7647,7 +7650,7 @@
 	(compare:CCC
 	  (plus:SI
 	    (match_operand:SI 1 "nonimmediate_operand" "%0")
-	    (match_operand:SI 2 "x86_64_general_operand" "rme"))
+	    (match_operand:SI 2 "x86_64_general_operand" "rBMe"))
 	  (match_dup 1)))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
@@ -7674,7 +7677,7 @@
 	(compare:CCC
 	    (plus:SWI
 		(match_operand:SWI 1 "nonimmediate_operand" "%0,0")
-		(match_operand:SWI 2 "<general_operand>" "<r><i>,m"))
+		(match_operand:SWI 2 "<general_operand>" "<r><i>,<m>"))
 	    (match_dup 2)))
    (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
 	(plus:SWI (match_dup 1) (match_dup 2)))]
@@ -7688,7 +7691,7 @@
 	(compare:CCC
 	  (plus:SI
 	    (match_operand:SI 1 "nonimmediate_operand" "%0")
-	    (match_operand:SI 2 "x86_64_general_operand" "rme"))
+	    (match_operand:SI 2 "x86_64_general_operand" "rBMe"))
 	  (match_dup 2)))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI (plus:SI (match_dup 1) (match_dup 2))))]
@@ -8032,7 +8035,7 @@
   [(set (match_operand:SWIM248 0 "register_operand" "=r,r,r")
 	(mult:SWIM248
 	  (match_operand:SWIM248 1 "nonimmediate_operand" "%rm,rm,0")
-	  (match_operand:SWIM248 2 "<general_operand>" "K,<i>,mr")))
+	  (match_operand:SWIM248 2 "<general_operand>" "K,<i>,<m>r")))
    (clobber (reg:CC FLAGS_REG))]
   "!(MEM_P (operands[1]) && MEM_P (operands[2]))"
   "@
@@ -8068,7 +8071,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r,r,r")
 	(zero_extend:DI
 	  (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%rm,rm,0")
-		   (match_operand:SI 2 "x86_64_general_operand" "K,e,mr"))))
+		   (match_operand:SI 2 "x86_64_general_operand" "K,e,BMr"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT
    && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
@@ -9813,7 +9816,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI
 	  (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-		  (match_operand:SI 2 "x86_64_general_operand" "rme"))))
+		  (match_operand:SI 2 "x86_64_general_operand" "rBMe"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (AND, SImode, operands)"
   "and{l}\t{%2, %k0|%k0, %2}"
@@ -9823,7 +9826,7 @@
 (define_insn "*and<mode>_1"
   [(set (match_operand:SWI24 0 "nonimmediate_operand" "=rm,r,Ya,?k")
 	(and:SWI24 (match_operand:SWI24 1 "nonimmediate_operand" "%0,0,qm,k")
-		   (match_operand:SWI24 2 "<general_operand>" "r<i>,m,L,k")))
+		   (match_operand:SWI24 2 "<general_operand>" "r<i>,<m>,L,k")))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (AND, <MODE>mode, operands)"
   "@
@@ -10005,7 +10008,7 @@
   [(set (reg FLAGS_REG)
 	(compare (and:SI
 		  (match_operand:SI 1 "nonimmediate_operand" "%0")
-		  (match_operand:SI 2 "x86_64_general_operand" "rme"))
+		  (match_operand:SI 2 "x86_64_general_operand" "rBMe"))
 		 (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI (and:SI (match_dup 1) (match_dup 2))))]
@@ -10048,7 +10051,7 @@
   [(set (reg FLAGS_REG)
 	(compare (and:SWI124
 		  (match_operand:SWI124 1 "nonimmediate_operand" "%0,0")
-		  (match_operand:SWI124 2 "<general_operand>" "<r><i>,m"))
+		  (match_operand:SWI124 2 "<general_operand>" "<r><i>,<m>"))
 		 (const_int 0)))
    (set (match_operand:SWI124 0 "nonimmediate_operand" "=<r>m,<r>")
 	(and:SWI124 (match_dup 1) (match_dup 2)))]
@@ -10362,7 +10365,7 @@
   [(set (match_operand:SWI248 0 "nonimmediate_operand" "=rm,r,?k")
 	(any_or:SWI248
 	 (match_operand:SWI248 1 "nonimmediate_operand" "%0,0,k")
-	 (match_operand:SWI248 2 "<general_operand>" "r<i>,m,k")))
+	 (match_operand:SWI248 2 "<general_operand>" "r<i>,<m>,k")))
    (clobber (reg:CC FLAGS_REG))]
   "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
   "@
@@ -10430,7 +10433,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI
 	 (any_or:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-		    (match_operand:SI 2 "x86_64_general_operand" "rme"))))
+		    (match_operand:SI 2 "x86_64_general_operand" "rBMe"))))
    (clobber (reg:CC FLAGS_REG))]
   "TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
   "<logic>{l}\t{%2, %k0|%k0, %2}"
@@ -10533,7 +10536,7 @@
   [(set (reg FLAGS_REG)
 	(compare (any_or:SWI
 		  (match_operand:SWI 1 "nonimmediate_operand" "%0,0")
-		  (match_operand:SWI 2 "<general_operand>" "<r><i>,m"))
+		  (match_operand:SWI 2 "<general_operand>" "<r><i>,<m>"))
 		 (const_int 0)))
    (set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
 	(any_or:SWI (match_dup 1) (match_dup 2)))]
@@ -10548,7 +10551,7 @@
 (define_insn "*<code>si_2_zext"
   [(set (reg FLAGS_REG)
 	(compare (any_or:SI (match_operand:SI 1 "nonimmediate_operand" "%0")
-			    (match_operand:SI 2 "x86_64_general_operand" "rme"))
+			    (match_operand:SI 2 "x86_64_general_operand" "rBMe"))
 		 (const_int 0)))
    (set (match_operand:DI 0 "register_operand" "=r")
 	(zero_extend:DI (any_or:SI (match_dup 1) (match_dup 2))))]