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| author | Haochen Jiang <haochen.jiang@intel.com> | 2021-12-01 16:48:28 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2021-12-15 16:26:14 +0800 |
| commit | 8f9fea41a767f6ad8cf3d521031048a2491f98b1 (patch) | |
| tree | 656d89a628e8794d43d0bb81ce8daca9b4eebf15 /gcc/config/i386 | |
| parent | 575ad7700f3d29d9310a778818c0c7a360f4eb1a (diff) | |
| download | gcc-8f9fea41a767f6ad8cf3d521031048a2491f98b1.zip gcc-8f9fea41a767f6ad8cf3d521031048a2491f98b1.tar.gz gcc-8f9fea41a767f6ad8cf3d521031048a2491f98b1.tar.bz2 | |
Add combine splitter to transform vashr/vlshr/vashl_optab to ashr/lshr/ashl_optab for const vector duplicate operand.
gcc/ChangeLog:
PR target/101796
* config/i386/predicates.md (const_vector_operand):
Add new predicate.
* config/i386/sse.md(<insn><mode>3<mask_name>):
Add new define_split below.
gcc/testsuite/ChangeLog:
PR target/101796
* gcc.target/i386/pr101796-1.c: New test.
Diffstat (limited to 'gcc/config/i386')
| -rw-r--r-- | gcc/config/i386/predicates.md | 13 | ||||
| -rw-r--r-- | gcc/config/i386/sse.md | 14 |
2 files changed, 27 insertions, 0 deletions
diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index 4ccbe11..770e2f0 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1844,6 +1844,19 @@ return true; }) +;; Return true if OP is a const vector with duplicate value. +(define_predicate "const_vector_duplicate_operand" + (match_code "const_vector") +{ + rtx elt = XVECEXP (op, 0, 0); + int i, nelt = XVECLEN (op, 0); + + for (i = 1; i < nelt; ++i) + if (!rtx_equal_p (elt, XVECEXP (op, 0, i))) + return false; + return true; +}) + ;; Return true if OP is a parallel for a vbroadcast permute. (define_predicate "avx_vbroadcast_operand" (and (match_code "parallel") diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 929eef5..768a93e 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -15287,6 +15287,20 @@ (const_string "0"))) (set_attr "mode" "<sseinsnmode>")]) +;; PR target/101796: Transfrom movl+vpbranchcastw+vpsravw to vpsraw +;; when COUNT is immediate. +(define_split + [(set (match_operand:VI248_AVX512BW 0 "register_operand") + (any_shift:VI248_AVX512BW + (match_operand:VI248_AVX512BW 1 "nonimmediate_operand") + (match_operand:VI248_AVX512BW 2 "const_vector_duplicate_operand")))] + "TARGET_AVX512F && GET_MODE_UNIT_BITSIZE (<MODE>mode) + > INTVAL (XVECEXP (operands[2], 0, 0))" + [(set (match_dup 0) + (any_shift:VI248_AVX512BW + (match_dup 1) + (match_dup 3)))] + "operands[3] = XVECEXP (operands[2], 0, 0);") (define_expand "vec_shl_<mode>" [(set (match_dup 3) |