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| author | Haochen Jiang <haochen.jiang@intel.com> | 2022-05-26 15:46:40 +0800 |
|---|---|---|
| committer | Haochen Jiang <haochen.jiang@intel.com> | 2022-10-21 10:42:00 +0800 |
| commit | 4e7ec7dbbbef3b4a83da5967b5f25e3be90c2dc6 (patch) | |
| tree | c16d74e647238e197e5d4faa63f9188186891d0b /gcc/config/i386 | |
| parent | 406675947d26ccbc2108e9689a2918bb36f61a63 (diff) | |
| download | gcc-4e7ec7dbbbef3b4a83da5967b5f25e3be90c2dc6.zip gcc-4e7ec7dbbbef3b4a83da5967b5f25e3be90c2dc6.tar.gz gcc-4e7ec7dbbbef3b4a83da5967b5f25e3be90c2dc6.tar.bz2 | |
i386: Auto vectorize sdot_prod, udot_prod with VNNIINT8 instruction.
gcc/ChangeLog:
* config/i386/sse.md (ssedvecmode): Rename from VI1SI.
(ssedvecmodelower): Rename from vi1si.
(sdot_prod<mode>): New define_expand.
(udot_prod<mode>): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/i386/vnniint8-auto-vectorize-1.c: New test.
* gcc.target/i386/vnniint8-auto-vectorize-2.c: Ditto.
Diffstat (limited to 'gcc/config/i386')
| -rw-r--r-- | gcc/config/i386/sse.md | 61 |
1 files changed, 50 insertions, 11 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 014b0b2..f4b5506 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1035,6 +1035,13 @@ (V16HI "v16hi") (V8HI "v8hi") (V32QI "v32qi") (V16QI "v16qi")]) +;; Mapping of vector modes to an V*SImode of the same size +(define_mode_attr ssedvecmode + [(V64QI "V16SI") (V32QI "V8SI") (V16QI "V4SI")]) + +(define_mode_attr ssedvecmodelower + [(V64QI "v16si") (V32QI "v8si") (V16QI "v4si")]) + ;; Mapping of vector modes to a vector mode of double size (define_mode_attr ssedoublevecmode [(V64QI "V128QI") (V32HI "V64HI") (V16SI "V32SI") (V8DI "V16DI") @@ -28509,29 +28516,23 @@ [(set_attr ("prefix") ("evex")) (set_attr "mode" "<sseinsnmode>")]) -(define_mode_attr VI1SI - [(V64QI "V16SI") (V32QI "V8SI") (V16QI "V4SI")]) - -(define_mode_attr vi1si - [(V64QI "v16si") (V32QI "v8si") (V16QI "v4si")]) - (define_expand "usdot_prod<mode>" - [(match_operand:<VI1SI> 0 "register_operand") + [(match_operand:<ssedvecmode> 0 "register_operand") (match_operand:VI1_AVX512VNNI 1 "register_operand") (match_operand:VI1_AVX512VNNI 2 "register_operand") - (match_operand:<VI1SI> 3 "register_operand")] + (match_operand:<ssedvecmode> 3 "register_operand")] "(<MODE_SIZE> == 64 ||((TARGET_AVX512VNNI && TARGET_AVX512VL) || TARGET_AVXVNNI))" { - operands[1] = lowpart_subreg (<VI1SI>mode, + operands[1] = lowpart_subreg (<ssedvecmode>mode, force_reg (<MODE>mode, operands[1]), <MODE>mode); - operands[2] = lowpart_subreg (<VI1SI>mode, + operands[2] = lowpart_subreg (<ssedvecmode>mode, force_reg (<MODE>mode, operands[2]), <MODE>mode); emit_insn (gen_rtx_SET (operands[0], operands[3])); - emit_insn (gen_vpdpbusd_<vi1si> (operands[0], operands[3], + emit_insn (gen_vpdpbusd_<ssedvecmodelower> (operands[0], operands[3], operands[1], operands[2])); DONE; }) @@ -29256,6 +29257,44 @@ (UNSPEC_VPDPBSUD "bsud") (UNSPEC_VPDPBSUDS "bsuds") (UNSPEC_VPDPBUUD "buud") (UNSPEC_VPDPBUUDS "buuds")]) +(define_expand "sdot_prod<mode>" + [(match_operand:<ssedvecmode> 0 "register_operand") + (match_operand:VI1 1 "register_operand") + (match_operand:VI1 2 "register_operand") + (match_operand:<ssedvecmode> 3 "register_operand")] + "TARGET_AVXVNNIINT8" +{ + operands[1] = lowpart_subreg (<ssedvecmode>mode, + force_reg (<MODE>mode, operands[1]), + <MODE>mode); + operands[2] = lowpart_subreg (<ssedvecmode>mode, + force_reg (<MODE>mode, operands[2]), + <MODE>mode); + emit_insn (gen_rtx_SET (operands[0], operands[3])); + emit_insn (gen_vpdpbssd_<ssedvecmodelower> (operands[0], operands[3], + operands[1], operands[2])); + DONE; +}) + +(define_expand "udot_prod<mode>" + [(match_operand:<ssedvecmode> 0 "register_operand") + (match_operand:VI1 1 "register_operand") + (match_operand:VI1 2 "register_operand") + (match_operand:<ssedvecmode> 3 "register_operand")] + "TARGET_AVXVNNIINT8" +{ + operands[1] = lowpart_subreg (<ssedvecmode>mode, + force_reg (<MODE>mode, operands[1]), + <MODE>mode); + operands[2] = lowpart_subreg (<ssedvecmode>mode, + force_reg (<MODE>mode, operands[2]), + <MODE>mode); + emit_insn (gen_rtx_SET (operands[0], operands[3])); + emit_insn (gen_vpdpbuud_<ssedvecmodelower> (operands[0], operands[3], + operands[1], operands[2])); + DONE; +}) + (define_insn "vpdp<vpdotprodtype>_<mode>" [(set (match_operand:VI4_AVX 0 "register_operand" "=x") (unspec:VI4_AVX |