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| author | Haochen Jiang <haochen.jiang@intel.com> | 2021-12-30 15:47:58 +0800 |
|---|---|---|
| committer | liuhongt <hongtao.liu@intel.com> | 2022-01-11 10:10:14 +0800 |
| commit | 4bb79e27c02c5cd57d5781bef20e70982d898c40 (patch) | |
| tree | 388319e806c74b1fc14e98abcb281064637ccc74 /gcc/config/i386 | |
| parent | d9450aa0e8b70f2362925cbcac8a29733899d37f (diff) | |
| download | gcc-4bb79e27c02c5cd57d5781bef20e70982d898c40.zip gcc-4bb79e27c02c5cd57d5781bef20e70982d898c40.tar.gz gcc-4bb79e27c02c5cd57d5781bef20e70982d898c40.tar.bz2 | |
Extend predicate of operands[1] from register_operand to vector_operand for andnot insn.
This can do optimization like
- pcmpeqd %xmm0, %xmm0
- pxor g(%rip), %xmm0
- pand %xmm1, %xmm0
+ movdqa g(%rip), %xmm0
+ pandn %xmm1, %xmm0
gcc/ChangeLog:
PR target/53652
* config/i386/sse.md (*andnot<mode>3): Extend predicate of
operands[1] from register_operand to vector_operand.
gcc/testsuite/ChangeLog:
PR target/53652
* gcc.target/i386/pr53652-1.c: New test.
Diffstat (limited to 'gcc/config/i386')
| -rw-r--r-- | gcc/config/i386/sse.md | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index d8f3035..0864748 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -16631,7 +16631,7 @@ (define_insn "*andnot<mode>3" [(set (match_operand:VI 0 "register_operand" "=x,x,v") (and:VI - (not:VI (match_operand:VI 1 "register_operand" "0,x,v")) + (not:VI (match_operand:VI 1 "vector_operand" "0,x,v")) (match_operand:VI 2 "bcst_vector_operand" "xBm,xm,vmBr")))] "TARGET_SSE" { |