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author | Roger Sayle <roger@nextmovesoftware.com> | 2022-07-18 07:44:38 +0100 |
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committer | Roger Sayle <roger@nextmovesoftware.com> | 2022-07-18 07:44:38 +0100 |
commit | 2907bfc3412dd8aef6c6acc17f2152a4e0ac4979 (patch) | |
tree | 3fa532064cc1c2d1d393d0ad90905d3bd604f2fb /gcc/config/i386 | |
parent | 43c2505b31adfdef2214318484aaae987fd9e1e0 (diff) | |
download | gcc-2907bfc3412dd8aef6c6acc17f2152a4e0ac4979.zip gcc-2907bfc3412dd8aef6c6acc17f2152a4e0ac4979.tar.gz gcc-2907bfc3412dd8aef6c6acc17f2152a4e0ac4979.tar.bz2 |
PR target/106231: Optimize (any_extend:DI (ctz:SI ...)) on x86_64.
This patch resolves PR target/106231 by providing insns that recognize
(zero_extend:DI (ctz:SI ...)) and (sign_extend:DI (ctz:SI ...)). The
result of ctz:SI is always between 0 and 32 (or undefined), so
sign_extension is the same as zero_extension, and the result is already
extended in the destination register.
Things are a little complicated, because the existing implementation
of *ctzsi2 handles multiple cases, including false dependencies, which
we continue to support in this patch.
2022-07-18 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
PR target/106231
* config/i386/i386.md (*ctzsidi2_<s>ext): New insn_and_split
to recognize any_extend:DI of ctz:SI which is implicitly extended.
(*ctzsidi2_<s>ext_falsedep): New define_insn to model a DImode
extended ctz:SI that has preceding xor to break false dependency.
gcc/testsuite/ChangeLog
PR target/106231
* gcc.target/i386/pr106231-1.c: New test case.
* gcc.target/i386/pr106231-2.c: New test case.
Diffstat (limited to 'gcc/config/i386')
-rw-r--r-- | gcc/config/i386/i386.md | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 31637bd..9aaeb69 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -16431,6 +16431,66 @@ (set_attr "prefix_rep" "1") (set_attr "mode" "SI")]) +(define_insn_and_split "*ctzsidi2_<s>ext" + [(set (match_operand:DI 0 "register_operand" "=r") + (any_extend:DI + (ctz:SI + (match_operand:SI 1 "nonimmediate_operand" "rm")))) + (clobber (reg:CC FLAGS_REG))] + "TARGET_64BIT" +{ + if (TARGET_BMI) + return "tzcnt{l}\t{%1, %k0|%k0, %1}"; + else if (TARGET_CPU_P (GENERIC) + && !optimize_function_for_size_p (cfun)) + /* tzcnt expands to 'rep bsf' and we can use it even if !TARGET_BMI. */ + return "rep%; bsf{l}\t{%1, %k0|%k0, %1}"; + return "bsf{l}\t{%1, %k0|%k0, %1}"; +} + "(TARGET_BMI || TARGET_CPU_P (GENERIC)) + && TARGET_AVOID_FALSE_DEP_FOR_BMI && epilogue_completed + && optimize_function_for_speed_p (cfun) + && !reg_mentioned_p (operands[0], operands[1])" + [(parallel + [(set (match_dup 0) + (any_extend:DI (ctz:SI (match_dup 1)))) + (unspec [(match_dup 0)] UNSPEC_INSN_FALSE_DEP) + (clobber (reg:CC FLAGS_REG))])] + "ix86_expand_clear (operands[0]);" + [(set_attr "type" "alu1") + (set_attr "prefix_0f" "1") + (set (attr "prefix_rep") + (if_then_else + (ior (match_test "TARGET_BMI") + (and (not (match_test "optimize_function_for_size_p (cfun)")) + (match_test "TARGET_CPU_P (GENERIC)"))) + (const_string "1") + (const_string "0"))) + (set_attr "mode" "SI")]) + +(define_insn "*ctzsidi2_<s>ext_falsedep" + [(set (match_operand:DI 0 "register_operand" "=r") + (any_extend:DI + (ctz:SI + (match_operand:SI 1 "nonimmediate_operand" "rm")))) + (unspec [(match_operand:DI 2 "register_operand" "0")] + UNSPEC_INSN_FALSE_DEP) + (clobber (reg:CC FLAGS_REG))] + "TARGET_64BIT" +{ + if (TARGET_BMI) + return "tzcnt{l}\t{%1, %k0|%k0, %1}"; + else if (TARGET_CPU_P (GENERIC)) + /* tzcnt expands to 'rep bsf' and we can use it even if !TARGET_BMI. */ + return "rep%; bsf{l}\t{%1, %k0|%k0, %1}"; + else + gcc_unreachable (); +} + [(set_attr "type" "alu1") + (set_attr "prefix_0f" "1") + (set_attr "prefix_rep" "1") + (set_attr "mode" "SI")]) + (define_insn "bsr_rex64" [(set (reg:CCZ FLAGS_REG) (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "rm") |