RISC-V: Improve slide1up pattern.

This patch adds a second variant to implement the extract/slide1up
pattern.  In order to do a permutation like
<3, 4, 5, 6> from vectors <0, 1, 2, 3> and <4, 5, 6, 7>
we currently extract <3> from the first vector and re-insert it into the
second vector.  Unless register-file crossing latency is essentially
zero it should be preferable to first slide the second vector up by
one, then slide down the first vector by (nunits - 1).

gcc/ChangeLog:

	* config/riscv/riscv-protos.h (riscv_register_move_cost):
	Export.
	* config/riscv/riscv-v.cc (shuffle_extract_and_slide1up_patterns):
	Rename...
	(shuffle_off_by_one_patterns): ... to this and add slideup/slidedown
	variant.
	(expand_vec_perm_const_1): Call renamed function.
	* config/riscv/riscv.cc (riscv_secondary_memory_needed): Remove
	static.
	(riscv_register_move_cost): Add VR<->GR/FR handling.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/pr112599-2.c: Adjust test
	expectation.

0 files changed, 0 insertions, 0 deletions