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| author | Julia Koval <julia.koval@intel.com> | 2018-03-30 09:04:55 +0200 |
|---|---|---|
| committer | Julia Koval <jkoval@gcc.gnu.org> | 2018-03-30 09:04:55 +0200 |
| commit | 06be18e782b9497ffda6523786a38f13f1412e36 (patch) | |
| tree | 8c3f2c0998a8489aad317c398d8e2aceb0fb2fe3 /gcc/config/i386/x86-tune.def | |
| parent | 9cffc5a73ac75e2abbea637d3685c6f4f67a79d0 (diff) | |
| download | gcc-06be18e782b9497ffda6523786a38f13f1412e36.zip gcc-06be18e782b9497ffda6523786a38f13f1412e36.tar.gz gcc-06be18e782b9497ffda6523786a38f13f1412e36.tar.bz2 | |
Enable tuning options for skylake-avx512.
gcc/
PR target/84413
* x86-tune.def (movx, partial_reg_dependency): Enable for
m_SKYLAKE_AVX512.
From-SVN: r258972
Diffstat (limited to 'gcc/config/i386/x86-tune.def')
| -rw-r--r-- | gcc/config/i386/x86-tune.def | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/gcc/config/i386/x86-tune.def b/gcc/config/i386/x86-tune.def index 53d0e16..9843ed8 100644 --- a/gcc/config/i386/x86-tune.def +++ b/gcc/config/i386/x86-tune.def @@ -50,7 +50,7 @@ DEF_TUNE (X86_TUNE_SCHEDULE, "schedule", DEF_TUNE (X86_TUNE_PARTIAL_REG_DEPENDENCY, "partial_reg_dependency", m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_BONNELL | m_SILVERMONT | m_INTEL - | m_KNL | m_KNM | m_AMD_MULTIPLE | m_GENERIC) + | m_KNL | m_KNM | m_AMD_MULTIPLE | m_SKYLAKE_AVX512 | m_GENERIC) /* X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY: This knob promotes all store destinations to be 128bit to allow register renaming on 128bit SSE units, @@ -85,7 +85,7 @@ DEF_TUNE (X86_TUNE_PARTIAL_FLAG_REG_STALL, "partial_flag_reg_stall", DEF_TUNE (X86_TUNE_MOVX, "movx", m_PPRO | m_P4_NOCONA | m_CORE2 | m_NEHALEM | m_SANDYBRIDGE | m_BONNELL | m_SILVERMONT | m_KNL | m_KNM | m_INTEL - | m_GEODE | m_AMD_MULTIPLE | m_GENERIC) + | m_GEODE | m_AMD_MULTIPLE | m_SKYLAKE_AVX512 | m_GENERIC) /* X86_TUNE_MEMORY_MISMATCH_STALL: Avoid partial stores that are followed by full sized loads. */ |