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| author | Richard Henderson <rth@redhat.com> | 2007-03-26 17:30:32 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@gcc.gnu.org> | 2007-03-26 17:30:32 -0700 |
| commit | 24bfafbc9d95153f4ad59d6618eae963a83723a0 (patch) | |
| tree | 6a311a473b6819715b29447bec1588f0b5b71df9 /gcc/config/i386/sse.md | |
| parent | df12b78f89bbeb779078c5817f62129f9a9e9db6 (diff) | |
| download | gcc-24bfafbc9d95153f4ad59d6618eae963a83723a0.zip gcc-24bfafbc9d95153f4ad59d6618eae963a83723a0.tar.gz gcc-24bfafbc9d95153f4ad59d6618eae963a83723a0.tar.bz2 | |
re PR target/31361 (SSE2 generation bug with shifts)
PR target/31361
* config/i386/i386.c (IX86_BUILTIN_PSLLDQ128, IX86_BUILTIN_PSLLW128,
IX86_BUILTIN_PSLLD128, IX86_BUILTIN_PSLLQ128, IX86_BUILTIN_PSRAW128,
IX86_BUILTIN_PSRAD128, IX86_BUILTIN_PSRLW128, IX86_BUILTIN_PSRLD128,
IX86_BUILTIN_PSRLQ128): New.
(ix86_init_mmx_sse_builtins): Add them.
(ix86_expand_builtin): Expand them.
* config/i386/sse.md (ashr<mode>3, lshr<mode>3, ashl<mode>3): Make
operand 2 be TImode.
* config/i386/emmintrin.h (_mm_slli_epi64, _mm_srai_epi16,
_mm_srai_epi32, _mm_srli_epi16, _mm_srli_epi32,
_mm_srli_epi64): Mark __B const.
(_mm_srli_si128, _mm_srli_si128): Fix disabled inline versions.
(_mm_sll_epi16, _mm_sll_epi32, _mm_sll_epi64, _mm_sra_epi16,
_mm_sra_epi32, _mm_srl_epi16, _mm_srl_epi32, _mm_srl_epi64): Use
new two-vector shift builtins.
From-SVN: r123250
Diffstat (limited to 'gcc/config/i386/sse.md')
| -rw-r--r-- | gcc/config/i386/sse.md | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index cc123cc..3d00df8 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -3085,7 +3085,7 @@ [(set (match_operand:SSEMODE24 0 "register_operand" "=x") (ashiftrt:SSEMODE24 (match_operand:SSEMODE24 1 "register_operand" "0") - (match_operand:SI 2 "nonmemory_operand" "xi")))] + (match_operand:TI 2 "nonmemory_operand" "xn")))] "TARGET_SSE2" "psra<ssevecsize>\t{%2, %0|%0, %2}" [(set_attr "type" "sseishft") @@ -3095,7 +3095,7 @@ [(set (match_operand:SSEMODE248 0 "register_operand" "=x") (lshiftrt:SSEMODE248 (match_operand:SSEMODE248 1 "register_operand" "0") - (match_operand:SI 2 "nonmemory_operand" "xi")))] + (match_operand:TI 2 "nonmemory_operand" "xn")))] "TARGET_SSE2" "psrl<ssevecsize>\t{%2, %0|%0, %2}" [(set_attr "type" "sseishft") @@ -3105,7 +3105,7 @@ [(set (match_operand:SSEMODE248 0 "register_operand" "=x") (ashift:SSEMODE248 (match_operand:SSEMODE248 1 "register_operand" "0") - (match_operand:SI 2 "nonmemory_operand" "xi")))] + (match_operand:TI 2 "nonmemory_operand" "xn")))] "TARGET_SSE2" "psll<ssevecsize>\t{%2, %0|%0, %2}" [(set_attr "type" "sseishft") |