diff options
| author | Jakub Jelinek <jakub@gcc.gnu.org> | 2017-07-25 15:35:17 +0200 |
|---|---|---|
| committer | Jakub Jelinek <jakub@gcc.gnu.org> | 2017-07-25 15:35:17 +0200 |
| commit | 774cccdc1a36493ae6925148c08dfbdcb2789e0c (patch) | |
| tree | df9284c91a2cdb772aea9ba75ef021025723d3b2 /gcc/config/i386/constraints.md | |
| parent | b3afe7922ac31f1cec1f200e1259287938cbd7e9 (diff) | |
| download | gcc-774cccdc1a36493ae6925148c08dfbdcb2789e0c.zip gcc-774cccdc1a36493ae6925148c08dfbdcb2789e0c.tar.gz gcc-774cccdc1a36493ae6925148c08dfbdcb2789e0c.tar.bz2 | |
re PR target/81532 (insn does not satisfy its constraints: extract_constrain_insn, at recog.c:2213)
PR target/81532
* config/i386/constraints.md (Yd, Ye): Use ALL_SSE_REGS for
TARGET_AVX512DQ rather than TARGET_AVX512BW.
* gcc.target/i386/pr80833-3.c: New test.
* gcc.target/i386/avx512dq-pr81532.c: New test.
* gcc.target/i386/avx512bw-pr81532.c: New test.
From-SVN: r250520
Diffstat (limited to 'gcc/config/i386/constraints.md')
| -rw-r--r-- | gcc/config/i386/constraints.md | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md index f94e274..98c05c9 100644 --- a/gcc/config/i386/constraints.md +++ b/gcc/config/i386/constraints.md @@ -138,19 +138,19 @@ (define_register_constraint "Yd" "TARGET_INTER_UNIT_MOVES_TO_VEC - ? (TARGET_AVX512BW + ? (TARGET_AVX512DQ ? ALL_SSE_REGS : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) : NO_REGS" - "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.") + "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves to vector registers are enabled.") (define_register_constraint "Ye" "TARGET_INTER_UNIT_MOVES_FROM_VEC - ? (TARGET_AVX512BW + ? (TARGET_AVX512DQ ? ALL_SSE_REGS : (TARGET_SSE4_1 ? SSE_REGS : NO_REGS)) : NO_REGS" - "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512BW target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.") + "@internal Any EVEX encodable SSE register (@code{%xmm0-%xmm31}) for AVX512DQ target or any SSE register for SSE4_1 target, when inter-unit moves from vector registers are enabled.") (define_register_constraint "Ym" "TARGET_MMX && TARGET_INTER_UNIT_MOVES_TO_VEC ? MMX_REGS : NO_REGS" |