Consolidate a couple peepholes and improve peepholes that combine stack allocations with stack stores.

	* config/h8300/h8300.md (SFI iterator): New iterator for
	SFmode and SImode.
	* config/h8300/peepholes.md (memory comparison): Use mode
	iterator to consolidate 3 patterns into one.
	(stack allocation and stack store): Handle SFmode.  Handle
	8 byte allocations.

2 files changed, 34 insertions, 41 deletions

diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md
index e9b598d..46ab244 100644
--- a/gcc/config/h8300/h8300.md
+++ b/gcc/config/h8300/h8300.md
@@ -191,6 +191,8 @@
 
 (define_mode_iterator QHSIF [QI HI SI SF])
 
+(define_mode_iterator SFI [SF SI])
+
 (define_code_iterator shifts [ashift ashiftrt lshiftrt])
 
 (define_code_iterator ors [ior xor])
diff --git a/gcc/config/h8300/peepholes.md b/gcc/config/h8300/peepholes.md
index 9086bdd..a0f5af2 100644
--- a/gcc/config/h8300/peepholes.md
+++ b/gcc/config/h8300/peepholes.md
@@ -551,9 +551,9 @@
 ;; Convert a memory comparison to a move if there is a scratch register.
 
 (define_peephole2
-  [(match_scratch:QI 1 "r")
+  [(match_scratch:QHSI 1 "r")
    (set (cc0)
-	(compare (match_operand:QI 0 "memory_operand" "")
+	(compare (match_operand:QHSI 0 "memory_operand" "")
 		 (const_int 0)))]
   ""
   [(set (match_dup 1)
@@ -562,31 +562,6 @@
 		       (const_int 0)))]
   "")
 
-(define_peephole2
-  [(match_scratch:HI 1 "r")
-   (set (cc0)
-	(compare (match_operand:HI 0 "memory_operand" "")
-		 (const_int 0)))]
-  ""
-  [(set (match_dup 1)
-	(match_dup 0))
-   (set (cc0) (compare (match_dup 1)
-		       (const_int 0)))]
-  "")
-
-(define_peephole2
-  [(match_scratch:SI 1 "r")
-   (set (cc0)
-	(compare (match_operand:SI 0 "memory_operand" "")
-		 (const_int 0)))]
-  ""
-  [(set (match_dup 1)
-	(match_dup 0))
-   (set (cc0) (compare (match_dup 1)
-		       (const_int 0)))]
-  "")
-
-
 ;; (compare (reg:HI) (const_int)) takes 4 bytes, so we try to achieve
 ;; the equivalent with shorter sequences.  Here is the summary.  Cases
 ;; are grouped for each define_peephole2.
@@ -1418,31 +1393,48 @@
 
 ;; stack adjustment of -4, generate one push
 ;;
-;; before : 6 bytes, 10 clocks
-;; after  : 4 bytes, 10 clocks
+;; before : 6 bytes
+;; after  : 4 bytes
 
 (define_peephole2
   [(set (reg:SI SP_REG)
 	(plus:SI (reg:SI SP_REG)
 		 (const_int -4)))
-   (set (mem:SI (reg:SI SP_REG))
-	(match_operand:SI 0 "register_operand" ""))]
+   (set (mem:SFI (reg:SI SP_REG))
+	(match_operand:SFI 0 "register_operand" ""))]
   "!TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
-  [(set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
-	(match_dup 0))]
-  "")
+  [(set (mem:SFI (pre_dec:SI (reg:SI SP_REG)))
+	(match_dup 0))])
+
+;; stack adjustment of -8, generate one push
+;;
+;; before : 8 bytes
+;; after  : 6 bytes
+
+(define_peephole2
+  [(set (reg:SI SP_REG)
+	(plus:SI (reg:SI SP_REG)
+		 (const_int -8)))
+   (set (mem:SFI (reg:SI SP_REG))
+	(match_operand:SFI 0 "register_operand" ""))]
+  "!TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
+  [(set (reg:SI SP_REG)
+	(plus:SI (reg:SI SP_REG)
+		 (const_int -4)))
+   (set (mem:SFI (pre_dec:SI (reg:SI SP_REG)))
+	(match_dup 0))])
 
 ;; stack adjustment of -12, generate one push
 ;;
-;; before : 10 bytes, 14 clocks
-;; after  :  8 bytes, 14 clocks
+;; before : 10 bytes
+;; after  :  8 bytes
 
 (define_peephole2
   [(set (reg:SI SP_REG)
 	(plus:SI (reg:SI SP_REG)
 		 (const_int -12)))
-   (set (mem:SI (reg:SI SP_REG))
-	(match_operand:SI 0 "register_operand" ""))]
+   (set (mem:SFI (reg:SI SP_REG))
+	(match_operand:SFI 0 "register_operand" ""))]
   "!TARGET_NORMAL_MODE && REGNO (operands[0]) != SP_REG"
   [(set (reg:SI SP_REG)
 	(plus:SI (reg:SI SP_REG)
@@ -1450,9 +1442,8 @@
    (set (reg:SI SP_REG)
 	(plus:SI (reg:SI SP_REG)
 		 (const_int -4)))
-   (set (mem:SI (pre_dec:SI (reg:SI SP_REG)))
-	(match_dup 0))]
-  "")
+   (set (mem:SFI (pre_dec:SI (reg:SI SP_REG)))
+	(match_dup 0))])
 
 ;; Transform
 ;;