diff options
author | Jeff Law <law@gcc.gnu.org> | 1996-04-30 23:49:58 -0600 |
---|---|---|
committer | Jeff Law <law@gcc.gnu.org> | 1996-04-30 23:49:58 -0600 |
commit | e1aa1a6c6e6d3f2771b9e0c369809265dd131fad (patch) | |
tree | beafe1473adea3226ae92c40292211ba35030872 /gcc/config/h8300 | |
parent | df37d0faf5643ad2f563c12d3a5c4a853a4cfb62 (diff) | |
download | gcc-e1aa1a6c6e6d3f2771b9e0c369809265dd131fad.zip gcc-e1aa1a6c6e6d3f2771b9e0c369809265dd131fad.tar.gz gcc-e1aa1a6c6e6d3f2771b9e0c369809265dd131fad.tar.bz2 |
h8300.md (bcs type): Remove "bcs" type attribute and all references.
* h8300/h8300.md (bcs type): Remove "bcs" type attribute and
all references.
(bcs insns): Delete. No longer needed.
(setcc from bitfield): Rewrite to use zero_extract. Provide
QImode, HImode and SImode variants.
From-SVN: r11910
Diffstat (limited to 'gcc/config/h8300')
-rw-r--r-- | gcc/config/h8300/h8300.md | 193 |
1 files changed, 24 insertions, 169 deletions
diff --git a/gcc/config/h8300/h8300.md b/gcc/config/h8300/h8300.md index f490310..b4fba57 100644 --- a/gcc/config/h8300/h8300.md +++ b/gcc/config/h8300/h8300.md @@ -45,7 +45,7 @@ ;; ??? Implement remaining bit ops available on the h8300 -(define_attr "type" "branch,bcs,arith" +(define_attr "type" "branch,arith" (const_string "arith")) ;; The size of instructions in bytes. @@ -63,29 +63,7 @@ (le (minus (pc) (match_dup 0)) (const_int 32000)))) (const_int 4) - (const_int 6))) - (eq_attr "type" "bcs") - (if_then_else (and (ge (minus (pc) (match_dup 0)) - (const_int -120)) - (le (minus (pc) (match_dup 0)) - (const_int 120))) - (if_then_else - (match_operand 2 "register_operand" "") - (const_int 4) - (const_int 6)) - (if_then_else (and (eq_attr "cpu" "h8300h") - (and (ge (minus (pc) (match_dup 0)) - (const_int -32000)) - (le (minus (pc) (match_dup 0)) - (const_int 32000)))) - (if_then_else - (match_operand 2 "register_operand" "") - (const_int 6) - (const_int 8)) - (if_then_else - (match_operand 2 "register_operand" "") - (const_int 8) - (const_int 10))))] + (const_int 6)))] (const_int 200))) ;; Condition code settings. @@ -460,13 +438,32 @@ ;; ---------------------------------------------------------------------- (define_insn "" - [(set (cc0) (and:QI (match_operand:QI 0 "bit_operand" "Ur") - (match_operand:QI 1 "o_operand" "O")))] + [(set (cc0) (zero_extract:QI (match_operand:HI 0 "register_operand" "r") + (const_int 1) + (match_operand:HI 1 "const_int_operand" "n")))] "" - "btst %W1,%R0" + "btst %Z1,%R0" [(set_attr "length" "2") (set_attr "cc" "set_zn_c0")]) +(define_insn "" + [(set (cc0) (zero_extract:HI (match_operand:HI 0 "register_operand" "r") + (const_int 1) + (match_operand:HI 1 "const_int_operand" "n")))] + "" + "btst %Z1,%Y0" + [(set_attr "length" "2") + (set_attr "cc" "set_zn_c0")]) + +(define_insn "" + [(set (cc0) (zero_extract:SI (match_operand:HI 0 "register_operand" "r") + (const_int 1) + (match_operand:HI 1 "const_int_operand" "n")))] + "" + "btst %Z1,%Y0" + [(set_attr "length" "2") + (set_attr "cc" "set_zn_c0")]) + (define_insn "tstqi" [(set (cc0) (match_operand:QI 0 "register_operand" "r"))] "" @@ -1825,148 +1822,6 @@ ;; The H8/300 has given 1/8th of its opcode space to bitfield ;; instructions so let's use them as well as we can. -;; BCC and BCS patterns. - -(define_insn "" - [(set (pc) - (if_then_else - (match_operator 1 "eq_operator" - [(zero_extract:QI - (match_operand:HI 2 "register_operand" "r") - (const_int 1) - (match_operand:HI 3 "immediate_operand" "i")) - (const_int 0)]) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* -{ - /* The length of this insn includes the bld insn below. We - compute the length of the branch without the bld so we - can easily choose the right branch length. */ - int branch_length = get_attr_length (insn); - - if (! register_operand (operands[2], HImode)) - branch_length -= 4; - else - branch_length -= 2; - - output_asm_insn(\"bld %Z3,%Y2\", operands); - if (branch_length == 2) - return \"%d1 %l0\"; - else if (branch_length == 4) - return \"%d1 %l0:16\"; - else - return \"%g1 %L0\;jmp @%l0\;%L0:\"; -}" - [(set_attr "type" "bcs") - (set_attr "cc" "clobber")]) - -(define_insn "" - [(set (pc) - (if_then_else - (match_operator 1 "eq_operator" - [(zero_extract:HI - (match_operand:HI 2 "register_operand" "r") - (const_int 1) - (match_operand:HI 3 "immediate_operand" "i")) - (const_int 0)]) - (label_ref (match_operand 0 "" "")) - (pc)))] - "" - "* -{ - /* The length of this insn includes the bld insn below. We - compute the length of the branch without the bld so we - can easily choose the right branch length. */ - int branch_length = get_attr_length (insn); - - if (! register_operand (operands[2], HImode)) - branch_length -= 4; - else - branch_length -= 2; - - output_asm_insn(\"bld %Z3,%Y2\", operands); - if (branch_length == 2) - return \"%d1 %l0\"; - else if (branch_length == 4) - return \"%d1 %l0:16\"; - else - return \"%g1 %L0\;jmp @%l0\;%L0:\"; -}" - [(set_attr "type" "bcs") - (set_attr "cc" "clobber")]) - -(define_insn "" - [(set (pc) - (if_then_else - (match_operator 1 "eq_operator" - [(zero_extract:HI - (match_operand:HI 2 "register_operand" "U") - (const_int 1) - (match_operand:HI 3 "immediate_operand" "i")) - (const_int 0)]) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* -{ - /* The length of this insn includes the bld insn below. We - compute the length of the branch without the bld so we - can easily choose the right branch length. */ - int branch_length = get_attr_length (insn); - - if (! register_operand (operands[2], HImode)) - branch_length -= 4; - else - branch_length -= 2; - - output_asm_insn(\"bld %Z3,%Y2\", operands); - if (branch_length == 2) - return \"%d1 %l0\"; - else if (branch_length == 4) - return \"%d1 %l0:16\"; - else - return \"%g1 %L0\;jmp @%l0\;%L0:\"; -}" - [(set_attr "type" "bcs") - (set_attr "cc" "clobber")]) - -(define_insn "" - [(set (pc) - (if_then_else - (match_operator 1 "eq_operator" - [(zero_extract:QI - (match_operand:HI 2 "register_operand" "r") - (const_int 1) - (match_operand:HI 3 "immediate_operand" "i")) - (const_int 0)]) - (pc) - (label_ref (match_operand 0 "" ""))))] - "" - "* -{ - /* The length of this insn includes the bld insn below. We - compute the length of the branch without the bld so we - can easily choose the right branch length. */ - int branch_length = get_attr_length (insn); - - if (! register_operand (operands[2], HImode)) - branch_length -= 4; - else - branch_length -= 2; - - output_asm_insn(\"bld %Z3,%Y2\", operands); - if (branch_length == 2) - return \"%d1 %l0\"; - else if (branch_length == 4) - return \"%d1 %l0:16\"; - else - return \"%g1 %L0\;jmp @%l0\;%L0:\"; -}" - [(set_attr "type" "bcs") - (set_attr "cc" "clobber")]) - ;; You'll never believe all these patterns perform one basic action -- ;; load a bit from the source, optionally invert the bit, then store it ;; in the destination (which is known to be zero).. |