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| author | Kazu Hirata <kazu@codesourcery.com> | 2007-02-20 02:26:06 +0000 |
|---|---|---|
| committer | Kazu Hirata <kazu@gcc.gnu.org> | 2007-02-20 02:26:06 +0000 |
| commit | a7b376eeb6b470b23a739038f57f0f2846fde1fb (patch) | |
| tree | c743bf814d7cb42b897746f31213730d00e36ae4 /gcc/config/fr30/fr30.md | |
| parent | a50aa827413db12b5a850b61f5a03546ac0381d3 (diff) | |
| download | gcc-a7b376eeb6b470b23a739038f57f0f2846fde1fb.zip gcc-a7b376eeb6b470b23a739038f57f0f2846fde1fb.tar.gz gcc-a7b376eeb6b470b23a739038f57f0f2846fde1fb.tar.bz2 | |
c4x.md, [...]: Follow spelling conventions.
* config/c4x/c4x.md, config/cris/cris.c, config/crx/crx.c,
config/fr30/fr30.md, config/i386/i386.h,
config/iq2000/iq2000.h, config/iq2000/predicates.md,
config/pa/milli64.S, config/pa/pa.c, config/pa/pa.h,
config/pa/pa.md, config/pa/pa32-regs.h, config/pa/pa64-regs.h,
config/pdp11/pdp11.c, config/pdp11/pdp11.h,
config/rs6000/altivec.md, config/rs6000/rs6000.c,
config/s390/s390-modes.def, config/sparc/netbsd-elf.h,
config/sparc/sparc.c, config/sparc/sparc.h,
config/sparc/sparc.md, config/spu/constraints.md,
config/spu/spu.c, config/stormy16/stormy16.md: Follow spelling
conventions.
From-SVN: r122151
Diffstat (limited to 'gcc/config/fr30/fr30.md')
| -rw-r--r-- | gcc/config/fr30/fr30.md | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/gcc/config/fr30/fr30.md b/gcc/config/fr30/fr30.md index c40a709..4e8e93a 100644 --- a/gcc/config/fr30/fr30.md +++ b/gcc/config/fr30/fr30.md @@ -746,7 +746,7 @@ ;;}}} ;;{{{ Multiplication -;; Signed multiplication producing 64 bit results from 32 bit inputs +;; Signed multiplication producing 64-bit results from 32-bit inputs (define_insn "mulsidi3" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%r")) @@ -757,7 +757,7 @@ [(set_attr "length" "6")] ) -;; Unsigned multiplication producing 64 bit results from 32 bit inputs +;; Unsigned multiplication producing 64-bit results from 32-bit inputs (define_insn "umulsidi3" [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r")) @@ -768,7 +768,7 @@ [(set_attr "length" "6")] ) -;; Signed multiplication producing 32 bit result from 16 bit inputs +;; Signed multiplication producing 32-bit result from 16-bit inputs (define_insn "mulhisi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (sign_extend:SI (match_operand:HI 1 "register_operand" "%r")) @@ -779,7 +779,7 @@ [(set_attr "length" "4")] ) -;; Unsigned multiplication producing 32 bit result from 16 bit inputs +;; Unsigned multiplication producing 32-bit result from 16-bit inputs (define_insn "umulhisi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "%r")) @@ -790,7 +790,7 @@ [(set_attr "length" "4")] ) -;; Signed multiplication producing 32 bit result from 32 bit inputs +;; Signed multiplication producing 32-bit result from 32-bit inputs (define_insn "mulsi3" [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_operand:SI 1 "register_operand" "%r") @@ -884,7 +884,7 @@ ;;}}} ;;{{{ Logical Operations -;; Logical AND, 32 bit integers +;; Logical AND, 32-bit integers (define_insn "andsi3" [(set (match_operand:SI 0 "register_operand" "=r") (and:SI (match_operand:SI 1 "register_operand" "%r") @@ -894,7 +894,7 @@ "and %1, %0" ) -;; Inclusive OR, 32 bit integers +;; Inclusive OR, 32-bit integers (define_insn "iorsi3" [(set (match_operand:SI 0 "register_operand" "=r") (ior:SI (match_operand:SI 1 "register_operand" "%r") @@ -904,7 +904,7 @@ "or %1, %0" ) -;; Exclusive OR, 32 bit integers +;; Exclusive OR, 32-bit integers (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=r") (xor:SI (match_operand:SI 1 "register_operand" "%r") @@ -914,7 +914,7 @@ "eor %1, %0" ) -;; One's complement, 32 bit integers +;; One's complement, 32-bit integers (define_expand "one_cmplsi2" [(set (match_operand:SI 0 "register_operand" "") (not:SI (match_operand:SI 1 "register_operand" "")))] @@ -1152,7 +1152,7 @@ ;; far away the destination is. ;; The calculation for the instruction length is derived as follows: -;; The branch instruction has a 9 bit signed displacement so we have +;; The branch instruction has a 9-bit signed displacement so we have ;; this inequality for the displacement: ;; ;; -256 <= pc < 256 |