RISC-V: Refine strided load/store testcase dump check to tree optimized

Like the sat alu related testcase, the dump check of strided load/store
takes the rtl dump for the standard name MASK_LEN_STRIDED_LOAD for times.
But the rtl pass expand is somehow mutable by the middle-end change or
debug information.

After that we need to adjust the dump check time and again.  This
patch would like to switch to tree optimized pass for the standard
name check, which is more stable up to a point.

The below test suites are passed for this patch.
* The rv64gcv fully regression test.

It is test only patch and obvious up to a point, will commit it
directly if no comments in next 48H.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f16.c: Take
	tree-optimized pass for standard name check, and adjust the times.
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f32.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-f64.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i16.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i32.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i64.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-i8.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u16.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u32.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u64.c: Ditto
	* gcc.target/riscv/rvv/autovec/strided/strided_ld_st-1-u8.c: Ditto

Signed-off-by: Pan Li <pan2.li@intel.com>

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