bpf: ISA V4 sign-extending move and load insns [PR110782,PR110784]

BPF ISA V4 introduces sign-extending move and load operations.  This
patch makes the BPF backend generate those instructions, when enabled
and useful.

A new option, -m[no-]smov gates generation of these instructions, and is
enabled by default for -mcpu=v4 and above.  Tests for the new
instructions and documentation for the new options are included.

	PR target/110782
	PR target/110784

gcc/

	* config/bpf/bpf.opt (msmov): New option.
	* config/bpf/bpf.cc (bpf_option_override): Handle it here.
	* config/bpf/bpf.md (*extendsidi2): New.
	(extendhidi2): New.
	(extendqidi2): New.
	(extendsisi2): New.
	(extendhisi2): New.
	(extendqisi2): New.
	* doc/invoke.texi (Option Summary): Add -msmov eBPF option.
	(eBPF Options): Add -m[no-]smov.  Document that -mcpu=v4
	also enables -msmov.

gcc/testsuite/

	* gcc.target/bpf/sload-1.c: New test.
	* gcc.target/bpf/sload-pseudoc-1.c: New test.
	* gcc.target/bpf/smov-1.c: New test.
	* gcc.target/bpf/smov-pseudoc-1.c: New test.

3 files changed, 57 insertions, 0 deletions

diff --git a/gcc/config/bpf/bpf.cc b/gcc/config/bpf/bpf.cc
index 0e07b41..b5b5674 100644
--- a/gcc/config/bpf/bpf.cc
+++ b/gcc/config/bpf/bpf.cc
@@ -262,6 +262,9 @@ bpf_option_override (void)
   if (bpf_has_sdiv == -1)
     bpf_has_sdiv = (bpf_isa >= ISA_V4);
 
+  if (bpf_has_smov == -1)
+    bpf_has_smov = (bpf_isa >= ISA_V4);
+
   /* Disable -fstack-protector as it is not supported in BPF.  */
   if (flag_stack_protect)
     {
diff --git a/gcc/config/bpf/bpf.md b/gcc/config/bpf/bpf.md
index 6643639..a69a239 100644
--- a/gcc/config/bpf/bpf.md
+++ b/gcc/config/bpf/bpf.md
@@ -307,6 +307,56 @@
   DONE;
 })
 
+;; ISA V4 introduces sign-extending move and load operations.
+
+(define_insn "*extendsidi2"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+        (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,q")))]
+  "bpf_has_smov"
+  "@
+   {movs\t%0,%1,32|%0 = (s32) %1}
+   {ldxsw\t%0,%1|%0 = *(s32 *) (%1)}"
+  [(set_attr "type" "alu,ldx")])
+
+(define_insn "extendhidi2"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+        (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "r,q")))]
+  "bpf_has_smov"
+  "@
+   {movs\t%0,%1,16|%0 = (s16) %1}
+   {ldxsh\t%0,%1|%0 = *(s16 *) (%1)}"
+  [(set_attr "type" "alu,ldx")])
+
+(define_insn "extendqidi2"
+  [(set (match_operand:DI 0 "register_operand" "=r,r")
+        (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "r,q")))]
+  "bpf_has_smov"
+  "@
+   {movs\t%0,%1,8|%0 = (s8) %1}
+   {ldxsb\t%0,%1|%0 = *(s8 *) (%1)}"
+  [(set_attr "type" "alu,ldx")])
+
+(define_insn "extendsisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (sign_extend:SI (match_operand:SI 1 "register_operand" "r")))]
+  "bpf_has_smov"
+  "{movs32\t%0,%1,32|%w0 = (s32) %w1}"
+  [(set_attr "type" "alu")])
+
+(define_insn "extendhisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
+  "bpf_has_smov"
+  "{movs32\t%0,%1,16|%w0 = (s16) %w1}"
+  [(set_attr "type" "alu")])
+
+(define_insn "extendqisi2"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
+  "bpf_has_smov"
+  "{movs32\t%0,%1,8|%w0 = (s8) %w1}"
+  [(set_attr "type" "alu")])
+
 ;;;; Data movement
 
 (define_mode_iterator MM [QI HI SI DI SF DF])
diff --git a/gcc/config/bpf/bpf.opt b/gcc/config/bpf/bpf.opt
index b21cfca..8e240d3 100644
--- a/gcc/config/bpf/bpf.opt
+++ b/gcc/config/bpf/bpf.opt
@@ -71,6 +71,10 @@ msdiv
 Target Var(bpf_has_sdiv) Init(-1)
 Enable signed division and modulus instructions.
 
+msmov
+Target Var(bpf_has_smov) Init(-1)
+Enable signed move and memory load instructions.
+
 mcpu=
 Target RejectNegative Joined Var(bpf_isa) Enum(bpf_isa) Init(ISA_V4)