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| author | Joern Rennecke <joern.rennecke@embecosm.com> | 2010-06-30 18:47:43 +0000 |
|---|---|---|
| committer | Joern Rennecke <amylaar@gcc.gnu.org> | 2010-06-30 19:47:43 +0100 |
| commit | a87cf97e0d6843f6ba6c4e120acfdb5693700eda (patch) | |
| tree | 684be6242471aff6286aab4d1043e3360a5902af /gcc/config/bfin | |
| parent | 6e44d26e24a11cfd8bfc929f2fbc2c73765c99af (diff) | |
| download | gcc-a87cf97e0d6843f6ba6c4e120acfdb5693700eda.zip gcc-a87cf97e0d6843f6ba6c4e120acfdb5693700eda.tar.gz gcc-a87cf97e0d6843f6ba6c4e120acfdb5693700eda.tar.bz2 | |
re PR middle-end/44566 (configuration with multiple targets / backends is not supported.)
PR other/44566
* coretypes.h [!USED_FOR_TARGET] (reg_class_t): Define.
* target.def (struct gcc_target): Replace enum reg_class with
reg_class_t in hook argument / return types.
* doc/tm.texi.in (TARGET_SECONDARY_RELOAD): Likewise.
(TARGET_IRA_COVER_CLASSES, TARGET_MEMORY_MOVE_COST): Likewise.
(TARGET_BRANCH_TARGET_REGISTER_CLASS): Likewise.
* targhooks.h (default_branch_target_register_class): Likewise.
(default_ira_cover_classes, default_secondary_reload): Likewise.
(default_memory_move_cost, default_register_move_cost): Likewise.
* targhooks.c (default_branch_target_register_class): Likewise.
(default_ira_cover_classes, default_secondary_reload): Likewise.
(default_memory_move_cost, default_register_move_cost): Likewise.
* reload.c (push_secondary_reload, secondary_reload_class): Likewise.
* bt-load.c (branch_target_load_optimize): Likewise.
* ira.c (setup_cover_and_important_classes): Likewise.
* ira-costs.c (copy_cost): Likewise.
* reload1.c (emit_input_reload_insns): Likewise.
* config/alpha/alpha.c (alpha_secondary_reload): Likewise.
* config/frv/frv.c (frv_secondary_reload): Likewise.
* config/s390/s390.c (s390_secondary_reload): Likewise.
* config/i386/i386.c (i386_ira_cover_classes): Likewise.
(ix86_secondary_reload, ix86_memory_move_cost): Likewise.
(ix86_register_move_cost): Likewise.
* config/sh/sh-protos.h (sh_secondary_reload): Likewise.
* config/sh/sh.c (sh_target_reg_class, sh_secondary_reload): Likewise.
* config/xtensa/xtensa.c (xtensa_secondary_reload): Likewise.
* config/xtensa/xtensa-protos.h (xtensa_secondary_reload): Likewise.
* config/rs6000/rs6000.c (rs6000_secondary_reload): Likewise.
(rs6000_ira_cover_classes): Likewise.
* config/picochip/picochip.c (picochip_secondary_reload): Likewise.
* config/picochip/picochip-protos.h (picochip_secondary_reload):
Likewise.
* config/pa/pa.c (pa_secondary_reload): Likewise.
* config/mips/mips.c (mips_ira_cover_classes): Likewise.
* config/bfin/bfin.c (bfin_secondary_reload): Likewise.
* config/ia64/ia64.c (ia64_register_move_cost): Likewise.
* doc/tm.texi: Regenerate.
From-SVN: r161633
Diffstat (limited to 'gcc/config/bfin')
| -rw-r--r-- | gcc/config/bfin/bfin.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c index c187bf3..1232ecc 100644 --- a/gcc/config/bfin/bfin.c +++ b/gcc/config/bfin/bfin.c @@ -2458,8 +2458,8 @@ bfin_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED, RCLASS requires an extra scratch register. Return the class needed for the scratch register. */ -static enum reg_class -bfin_secondary_reload (bool in_p, rtx x, enum reg_class rclass, +static reg_class_t +bfin_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, enum machine_mode mode, secondary_reload_info *sri) { /* If we have HImode or QImode, we can only use DREGS as secondary registers; @@ -2467,6 +2467,7 @@ bfin_secondary_reload (bool in_p, rtx x, enum reg_class rclass, enum reg_class default_class = GET_MODE_SIZE (mode) >= 4 ? DPREGS : DREGS; enum reg_class x_class = NO_REGS; enum rtx_code code = GET_CODE (x); + enum reg_class rclass = (enum reg_class) rclass_i; if (code == SUBREG) x = SUBREG_REG (x), code = GET_CODE (x); |