alpha.c (alpha_preferred_reload_class, [...]): Avoid C++ keywords.

	* config/alpha/alpha.c (alpha_preferred_reload_class,
	alpha_secondary_reload, alpha_emit_set_const_1, function_value,
	alpha_output_mi_thunk_osf): Avoid C++ keywords.
	* config/arm/arm.c (output_move_vfp, output_move_neon): Likewise.
	* config/arm/arm.md: Likewise.
	* config/avr/avr-protos.h (preferred_reload_class,
	test_hard_reg_class, avr_simplify_comparison_p,
	out_shift_with_cnt, class_max_nregs): Likewise.
	* config/avr/avr.c (class_max_nregs, avr_simplify_comparison_p,
	output_movqi, output_movhi, output_movsisf, out_shift_with_cnt,
	preferred_reload_class, test_hard_reg_class): Likewise.
	* config/bfin/bfin.c (legitimize_pic_address, hard_regno_mode_ok,
	bfin_memory_move_cost, bfin_secondary_reload,
	bfin_output_mi_thunk): Likewise.
	* config/crx/crx.c (crx_secondary_reload_class,
	crx_memory_move_cost): Likewise.
	* config/frv/frv-protos.h (frv_secondary_reload_class,
	frv_class_likely_spilled_p, frv_class_max_nregs): Likewise.
	* config/frv/frv.c (frv_override_options, frv_alloc_temp_reg,
	frv_secondary_reload_class, frv_class_likely_spilled_p,
	frv_class_max_nregs): Likewise.
	* config/h8300/h8300.c (h8300_classify_operand,
	h8300_unary_length, h8300_bitfield_length, h8300_asm_insn_count):
	Likewise.
	* config/i386/winnt.c (i386_pe_declare_function_type): Likewise.
	* config/ia64/ia64.c (ia64_preferred_reload_class,
	ia64_secondary_reload_class, ia64_output_mi_thunk): Likewise.
	* config/iq2000/iq2000.c (gen_int_relational): Likewise.
	* config/m32c/m32c.c (class_can_hold_mode, m32c_output_compare):
	Likewise.
	* config/m68hc11/m68hc11.c (preferred_reload_class,
	m68hc11_memory_move_cost): Likewise.
	* config/mcore/mcore.c (mcore_secondary_reload_class,
	mcore_reload_class): Likewise.
	* config/mips/mips.c (mips_hard_regno_mode_ok_p,
	mips_class_max_nregs, mips_cannot_change_mode_class,
	mips_preferred_reload_class, mips_secondary_reload_class,
	mips_output_mi_thunk): Likewise.
	* config/mmix/mmix.c (mmix_preferred_reload_class,
	mmix_preferred_output_reload_class, mmix_secondary_reload_class):
	Likewise.
	* config/mn10300/mn10300.c (mn10300_secondary_reload_class):
	Likewise.
	* config/pa/pa.c (pa_secondary_reload, pa_combine_instructions,
	pa_can_combine_p, pa_cannot_change_mode_class): Likewise.
	* config/pa/pa.h (LEGITIMIZE_RELOAD_ADDRESS): Likewise.
	* config/rs6000/rs6000.c (paired_expand_vector_init,
	rs6000_secondary_reload_class, rs6000_output_mi_thunk,
	compare_section_name, rs6000_memory_move_cost): Likewise.
	* config/s390/s390.c (s390_emit_compare_and_swap,
	s390_preferred_reload_class, s390_secondary_reload,
	legitimize_pic_address, legitimize_tls_address,
	legitimize_reload_address, s390_expand_cs_hqi, s390_expand_atomic,
	s390_class_max_nregs): Likewise.
	* config/s390/s390.h (LEGITIMIZE_RELOAD_ADDRESS): Likewise.
	* config/s390/s390.md: Likewise.
	* config/score/score-protos.h (score_secondary_reload_class,
	score_preferred_reload_class): Likewise.
	* config/score/score.c (score_preferred_reload_class,
	score_secondary_reload_class): Likewise.
	* config/score/score3.c (score3_output_mi_thunk,
	score3_preferred_reload_class, score3_secondary_reload_class,
	score3_hard_regno_mode_ok): Likewise.
	* config/score/score3.h (score3_preferred_reload_class,
	score3_secondary_reload_class): Likewise.
	* config/score/score7.c (score7_output_mi_thunk,
	score7_preferred_reload_class, score7_secondary_reload_class,
	score7_hard_regno_mode_ok): Likewise.
	* config/score/score7.h (score7_preferred_reload_class,
	score7_secondary_reload_class): Likewise.
	* config/sh/sh.c (prepare_move_operands, output_far_jump,
	output_branchy_insn, add_constant, gen_block_redirect,
	sh_insn_length_adjustment, sh_cannot_change_mode_class,
	sh_output_mi_thunk, replace_n_hard_rtx, sh_secondary_reload):
	Likewise.
	* config/sparc/sparc.c (sparc_output_mi_thunk): Likewise.
	* config/stormy16/stormy16.c (xstormy16_output_cbranch_hi,
	xstormy16_output_cbranch_si, xstormy16_secondary_reload_class,
	xstormy16_preferred_reload_class): Likewise.
	* config/xtensa/xtensa.c (xtensa_expand_compare_and_swap,
	xtensa_expand_atomic, override_options,
	xtensa_preferred_reload_class, xtensa_secondary_reload_class):
	Likewise.
	* reorg.c (try_merge_delay_insns): Likewise.
	* tree.c (merge_dllimport_decl_attributes): Likewise.

	* config/frv/frv.c (frv_print_operand): Change isalpha to ISALPHA.

From-SVN: r138813

1 files changed, 21 insertions, 21 deletions

diff --git a/gcc/config/bfin/bfin.c b/gcc/config/bfin/bfin.c
index 8437260..8fda5c0 100644
--- a/gcc/config/bfin/bfin.c
+++ b/gcc/config/bfin/bfin.c
@@ -279,7 +279,7 @@ static rtx
 legitimize_pic_address (rtx orig, rtx reg, rtx picreg)
 {
   rtx addr = orig;
-  rtx new = orig;
+  rtx new_rtx = orig;
 
   if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
     {
@@ -301,9 +301,9 @@ legitimize_pic_address (rtx orig, rtx reg, rtx picreg)
 	}
 
       tmp = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, addr), unspec);
-      new = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, picreg, tmp));
+      new_rtx = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, picreg, tmp));
 
-      emit_move_insn (reg, new);
+      emit_move_insn (reg, new_rtx);
       if (picreg == pic_offset_table_rtx)
 	crtl->uses_pic_offset_table = 1;
       return reg;
@@ -348,7 +348,7 @@ legitimize_pic_address (rtx orig, rtx reg, rtx picreg)
       return gen_rtx_PLUS (Pmode, base, addr);
     }
 
-  return new;
+  return new_rtx;
 }
 
 /* Stack frame layout. */
@@ -2156,14 +2156,14 @@ int
 hard_regno_mode_ok (int regno, enum machine_mode mode)
 {
   /* Allow only dregs to store value of mode HI or QI */
-  enum reg_class class = REGNO_REG_CLASS (regno);
+  enum reg_class rclass = REGNO_REG_CLASS (regno);
 
   if (mode == CCmode)
     return 0;
 
   if (mode == V2HImode)
     return D_REGNO_P (regno);
-  if (class == CCREGS)
+  if (rclass == CCREGS)
     return mode == BImode;
   if (mode == PDImode || mode == V2PDImode)
     return regno == REG_A0 || regno == REG_A1;
@@ -2232,24 +2232,24 @@ bfin_register_move_cost (enum machine_mode mode,
 
 int
 bfin_memory_move_cost (enum machine_mode mode ATTRIBUTE_UNUSED,
-		       enum reg_class class,
+		       enum reg_class rclass,
 		       int in ATTRIBUTE_UNUSED)
 {
   /* Make memory accesses slightly more expensive than any register-register
      move.  Also, penalize non-DP registers, since they need secondary
      reloads to load and store.  */
-  if (! reg_class_subset_p (class, DPREGS))
+  if (! reg_class_subset_p (rclass, DPREGS))
     return 10;
 
   return 8;
 }
 
 /* Inform reload about cases where moving X with a mode MODE to a register in
-   CLASS requires an extra scratch register.  Return the class needed for the
+   RCLASS requires an extra scratch register.  Return the class needed for the
    scratch register.  */
 
 static enum reg_class
-bfin_secondary_reload (bool in_p, rtx x, enum reg_class class,
+bfin_secondary_reload (bool in_p, rtx x, enum reg_class rclass,
 		       enum machine_mode mode, secondary_reload_info *sri)
 {
   /* If we have HImode or QImode, we can only use DREGS as secondary registers;
@@ -2280,11 +2280,11 @@ bfin_secondary_reload (bool in_p, rtx x, enum reg_class class,
       rtx op2 = XEXP (x, 1);
       int large_constant_p = ! satisfies_constraint_Ks7 (op2);
 
-      if (class == PREGS || class == PREGS_CLOBBERED)
+      if (rclass == PREGS || rclass == PREGS_CLOBBERED)
 	return NO_REGS;
       /* If destination is a DREG, we can do this without a scratch register
 	 if the constant is valid for an add instruction.  */
-      if ((class == DREGS || class == DPREGS)
+      if ((rclass == DREGS || rclass == DPREGS)
 	  && ! large_constant_p)
 	return NO_REGS;
       /* Reloading to anything other than a DREG?  Use a PREG scratch
@@ -2297,11 +2297,11 @@ bfin_secondary_reload (bool in_p, rtx x, enum reg_class class,
      AREGS are an exception; they can only move to or from another register
      in AREGS or one in DREGS.  They can also be assigned the constant 0.  */
   if (x_class == AREGS || x_class == EVEN_AREGS || x_class == ODD_AREGS)
-    return (class == DREGS || class == AREGS || class == EVEN_AREGS
-	    || class == ODD_AREGS
+    return (rclass == DREGS || rclass == AREGS || rclass == EVEN_AREGS
+	    || rclass == ODD_AREGS
 	    ? NO_REGS : DREGS);
 
-  if (class == AREGS || class == EVEN_AREGS || class == ODD_AREGS)
+  if (rclass == AREGS || rclass == EVEN_AREGS || rclass == ODD_AREGS)
     {
       if (code == MEM)
 	{
@@ -2318,15 +2318,15 @@ bfin_secondary_reload (bool in_p, rtx x, enum reg_class class,
     }
 
   /* CCREGS can only be moved from/to DREGS.  */
-  if (class == CCREGS && x_class != DREGS)
+  if (rclass == CCREGS && x_class != DREGS)
     return DREGS;
-  if (x_class == CCREGS && class != DREGS)
+  if (x_class == CCREGS && rclass != DREGS)
     return DREGS;
 
   /* All registers other than AREGS can load arbitrary constants.  The only
      case that remains is MEM.  */
   if (code == MEM)
-    if (! reg_class_subset_p (class, default_class))
+    if (! reg_class_subset_p (rclass, default_class))
       return default_class;
 
   return NO_REGS;
@@ -5127,12 +5127,12 @@ bfin_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
 {
   rtx xops[3];
   /* The this parameter is passed as the first argument.  */
-  rtx this = gen_rtx_REG (Pmode, REG_R0);
+  rtx this_rtx = gen_rtx_REG (Pmode, REG_R0);
 
   /* Adjust the this parameter by a fixed constant.  */
   if (delta)
     {
-      xops[1] = this;
+      xops[1] = this_rtx;
       if (delta >= -64 && delta <= 63)
 	{
 	  xops[0] = GEN_INT (delta);
@@ -5175,7 +5175,7 @@ bfin_output_mi_thunk (FILE *file ATTRIBUTE_UNUSED,
 	  output_asm_insn ("%h1 = %h0; %d1 = %d0; %2 = %2 + %1", xops);
 	  xops[0] = gen_rtx_MEM (Pmode, p2tmp);
 	}
-      xops[2] = this;
+      xops[2] = this_rtx;
       output_asm_insn ("%1 = %0; %2 = %2 + %1;", xops);
     }