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| author | Georg-Johann Lay <gjl@gcc.gnu.org> | 2012-10-05 16:37:04 +0000 |
|---|---|---|
| committer | Georg-Johann Lay <gjl@gcc.gnu.org> | 2012-10-05 16:37:04 +0000 |
| commit | 870128f21dafd76dcb45435ee3c88d21c27f9c63 (patch) | |
| tree | c32afe6efd8c70287032e9b32249cb410c0388d0 /gcc/config/avr | |
| parent | 8f2b580aeb950a7f2a8e95d16d79daa21f88143d (diff) | |
| download | gcc-870128f21dafd76dcb45435ee3c88d21c27f9c63.zip gcc-870128f21dafd76dcb45435ee3c88d21c27f9c63.tar.gz gcc-870128f21dafd76dcb45435ee3c88d21c27f9c63.tar.bz2 | |
avr.md: Fix indentations of insn C snippets.
* config/avr/avr.md: Fix indentations of insn C snippets.
From-SVN: r192136
Diffstat (limited to 'gcc/config/avr')
| -rw-r--r-- | gcc/config/avr/avr.md | 72 |
1 files changed, 36 insertions, 36 deletions
diff --git a/gcc/config/avr/avr.md b/gcc/config/avr/avr.md index d3ffd1a..19424b6 100644 --- a/gcc/config/avr/avr.md +++ b/gcc/config/avr/avr.md @@ -4167,13 +4167,13 @@ "reload_completed" [(set (match_dup 2) (match_dup 1)) (set (match_dup 3) (const_int 0))] -{ - unsigned int low_off = subreg_lowpart_offset (QImode, HImode); - unsigned int high_off = subreg_highpart_offset (QImode, HImode); + { + unsigned int low_off = subreg_lowpart_offset (QImode, HImode); + unsigned int high_off = subreg_highpart_offset (QImode, HImode); - operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off); - operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off); -}) + operands[2] = simplify_gen_subreg (QImode, operands[0], HImode, low_off); + operands[3] = simplify_gen_subreg (QImode, operands[0], HImode, high_off); + }) (define_insn_and_split "zero_extendqipsi2" [(set (match_operand:PSI 0 "register_operand" "=r") @@ -4198,13 +4198,13 @@ "reload_completed" [(set (match_dup 2) (zero_extend:HI (match_dup 1))) (set (match_dup 3) (const_int 0))] -{ - unsigned int low_off = subreg_lowpart_offset (HImode, SImode); - unsigned int high_off = subreg_highpart_offset (HImode, SImode); + { + unsigned int low_off = subreg_lowpart_offset (HImode, SImode); + unsigned int high_off = subreg_highpart_offset (HImode, SImode); - operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off); - operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off); -}) + operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off); + operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off); + }) (define_insn_and_split "zero_extendhipsi2" [(set (match_operand:PSI 0 "register_operand" "=r") @@ -4248,13 +4248,13 @@ "reload_completed" [(set (match_dup 2) (match_dup 1)) (set (match_dup 3) (const_int 0))] -{ - unsigned int low_off = subreg_lowpart_offset (HImode, SImode); - unsigned int high_off = subreg_highpart_offset (HImode, SImode); + { + unsigned int low_off = subreg_lowpart_offset (HImode, SImode); + unsigned int high_off = subreg_highpart_offset (HImode, SImode); - operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off); - operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off); -}) + operands[2] = simplify_gen_subreg (HImode, operands[0], SImode, low_off); + operands[3] = simplify_gen_subreg (HImode, operands[0], SImode, high_off); + }) (define_insn_and_split "zero_extendpsisi2" [(set (match_operand:SI 0 "register_operand" "=r") @@ -4277,13 +4277,13 @@ "reload_completed" [(set (match_dup 2) (zero_extend:SI (match_dup 1))) (set (match_dup 3) (const_int 0))] -{ - unsigned int low_off = subreg_lowpart_offset (SImode, DImode); - unsigned int high_off = subreg_highpart_offset (SImode, DImode); + { + unsigned int low_off = subreg_lowpart_offset (SImode, DImode); + unsigned int high_off = subreg_highpart_offset (SImode, DImode); - operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off); - operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off); -}) + operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off); + operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off); + }) (define_insn_and_split "zero_extendhidi2" [(set (match_operand:DI 0 "register_operand" "=r") @@ -4293,13 +4293,13 @@ "reload_completed" [(set (match_dup 2) (zero_extend:SI (match_dup 1))) (set (match_dup 3) (const_int 0))] -{ - unsigned int low_off = subreg_lowpart_offset (SImode, DImode); - unsigned int high_off = subreg_highpart_offset (SImode, DImode); + { + unsigned int low_off = subreg_lowpart_offset (SImode, DImode); + unsigned int high_off = subreg_highpart_offset (SImode, DImode); - operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off); - operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off); -}) + operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off); + operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off); + }) (define_insn_and_split "zero_extendsidi2" [(set (match_operand:DI 0 "register_operand" "=r") @@ -4309,13 +4309,13 @@ "reload_completed" [(set (match_dup 2) (match_dup 1)) (set (match_dup 3) (const_int 0))] -{ - unsigned int low_off = subreg_lowpart_offset (SImode, DImode); - unsigned int high_off = subreg_highpart_offset (SImode, DImode); + { + unsigned int low_off = subreg_lowpart_offset (SImode, DImode); + unsigned int high_off = subreg_highpart_offset (SImode, DImode); - operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off); - operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off); -}) + operands[2] = simplify_gen_subreg (SImode, operands[0], DImode, low_off); + operands[3] = simplify_gen_subreg (SImode, operands[0], DImode, high_off); + }) ;;<=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=><=> ;; compare |